soc/mediatek: move MSDC drivers to soc folder

Setting of MSDC is defined by soc, so we move them to soc folder.

TEST=emerge-cherry coreboot; emerge-asurada coreboot

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

4 files changed, 200 insertions, 2 deletions

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index e5ca4857fc..a75ac28b08 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -56,7 +56,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
-ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
+ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmif.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
diff --git a/src/soc/mediatek/mt8192/msdc.c b/src/soc/mediatek/mt8192/msdc.c
new file mode 100644
index 0000000000..113069a27b
--- /dev/null
+++ b/src/soc/mediatek/mt8192/msdc.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/gpio.h>
+#include <soc/regulator.h>
+#include <soc/msdc.h>
+
+#define MSDC0_BASE	0x11f60000
+#define MSDC0_TOP_BASE	0x11f50000
+
+#define MSDC0_DRV_MASK	0x3fffffff
+#define MSDC1_DRV_MASK	0x3ffff000
+#define MSDC0_DRV_VALUE	0x24924924
+#define MSDC1_DRV_VALUE	0x1b6db000
+
+#define MSDC1_GPIO_MODE0_BASE	0x10005360
+#define MSDC1_GPIO_MODE0_MASK	0x77777000
+#define MSDC1_GPIO_MODE0_VALUE	0x11111000
+
+#define MSDC1_GPIO_MODE1_BASE	0x10005370
+#define MSDC1_GPIO_MODE1_MASK	0x7
+#define MSDC1_GPIO_MODE1_VALUE	0x1
+
+void mtk_msdc_configure_emmc(bool is_early_init)
+{
+	void *gpio_base = (void *)IOCFG_TL_BASE;
+	int i;
+
+	const gpio_t emmc_pu_pin[] = {
+		GPIO(MSDC0_DAT0), GPIO(MSDC0_DAT1),
+		GPIO(MSDC0_DAT2), GPIO(MSDC0_DAT3),
+		GPIO(MSDC0_DAT4), GPIO(MSDC0_DAT5),
+		GPIO(MSDC0_DAT6), GPIO(MSDC0_DAT7),
+		GPIO(MSDC0_CMD), GPIO(MSDC0_RSTB),
+	};
+
+	const gpio_t emmc_pd_pin[] = {
+		GPIO(MSDC0_DSL), GPIO(MSDC0_CLK),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++)
+		gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++)
+		gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
+
+	/* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */
+	clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE);
+
+	if (is_early_init)
+		mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE);
+}
+
+void mtk_msdc_configure_sdcard(void)
+{
+	void *gpio_base = (void *)IOCFG_RM_BASE;
+	void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE;
+	void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE;
+	uint8_t enable = 1;
+	int i;
+
+	const gpio_t sdcard_pu_pin[] = {
+		GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1),
+		GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3),
+		GPIO(MSDC1_CMD),
+	};
+
+	const gpio_t sdcard_pd_pin[] = {
+		GPIO(MSDC1_CLK),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++)
+		gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++)
+		gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
+
+	/* set sdcard cmd/dat/clk pins driving to 8mA */
+	clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE);
+
+	/* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */
+	clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE);
+
+	/* set sdcard dat1 pin to msdc1 mode */
+	clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE);
+
+	mainboard_enable_regulator(MTK_REGULATOR_VCC, enable);
+	mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable);
+}
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index b22acf90a7..c6f4226ae3 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -68,7 +68,7 @@ ramstage-y += ../common/mcupm.c
 ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
 ramstage-y += mt6360.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
-ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
+ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c
 ramstage-y += ../common/pll.c pll.c
 ramstage-y += ../common/pmif.c
 ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
diff --git a/src/soc/mediatek/mt8195/msdc.c b/src/soc/mediatek/mt8195/msdc.c
new file mode 100644
index 0000000000..bbfeaa6c81
--- /dev/null
+++ b/src/soc/mediatek/mt8195/msdc.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
+#include <soc/regulator.h>
+#include <soc/msdc.h>
+#include <soc/mt6360.h>
+
+DEFINE_BITFIELD(MSDC0_DRV, 29, 0)
+DEFINE_BITFIELD(MSDC1_DRV, 17, 0)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8)
+DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12)
+
+#define MSDC0_BASE	0x11230000
+#define MSDC0_TOP_BASE	0x11f50000
+
+#define MSDC0_DRV_VALUE	0x1b6db6db
+#define MSDC1_DRV_VALUE	0x1b6db
+#define MSDC1_GPIO_MODE0_VALUE	0x1
+#define MSDC1_GPIO_MODE1_VALUE	0x1
+
+enum {
+	MSDC1_GPIO_MODE0_BASE = 0x100053d0,
+	MSDC1_GPIO_MODE1_BASE = 0x100053e0,
+};
+
+void mtk_msdc_configure_emmc(bool is_early_init)
+{
+	void *gpio_base = (void *)IOCFG_TL_BASE;
+	int i;
+
+	const gpio_t emmc_pu_pin[] = {
+		GPIO(EMMC_DAT0), GPIO(EMMC_DAT1),
+		GPIO(EMMC_DAT2), GPIO(EMMC_DAT3),
+		GPIO(EMMC_DAT4), GPIO(EMMC_DAT5),
+		GPIO(EMMC_DAT6), GPIO(EMMC_DAT7),
+		GPIO(EMMC_CMD), GPIO(EMMC_RSTB),
+	};
+
+	const gpio_t emmc_pd_pin[] = {
+		GPIO(EMMC_DSL), GPIO(EMMC_CLK),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++)
+		gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++)
+		gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
+
+	/* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */
+	SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE);
+
+	if (is_early_init)
+		mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE);
+}
+
+void mtk_msdc_configure_sdcard(void)
+{
+	void *gpio_base = (void *)IOCFG_RB_BASE;
+	void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE;
+	void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE;
+	int i;
+
+	const gpio_t sdcard_pu_pin[] = {
+		GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1),
+		GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3),
+		GPIO(MSDC1_CMD),
+	};
+
+	const gpio_t sdcard_pd_pin[] = {
+		GPIO(MSDC1_CLK),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++)
+		gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP);
+
+	for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++)
+		gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
+
+	/* set sdcard cmd/dat/clk pins driving to 8mA */
+	SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE);
+
+	/* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */
+	SET32_BITFIELDS(gpio_mode0_base,
+			MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE,
+			MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE);
+
+	/* set sdcard dat1 pin to msdc1 mode */
+	SET32_BITFIELDS(gpio_mode1_base,
+			MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE,
+			MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE,
+			MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE,
+			MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE);
+
+	mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST);
+
+	if (CONFIG(BOARD_GOOGLE_CHERRY))
+		mt6360_init(I2C7);
+
+	mainboard_enable_regulator(MTK_REGULATOR_VCCQ, 1);
+	mainboard_enable_regulator(MTK_REGULATOR_VCC, 1);
+}