diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-13 14:12:45 +0200 |
---|---|---|
committer | Alexander Couzens <lynxis@fe80.eu> | 2016-10-15 22:18:01 +0200 |
commit | c8c73a68beb199b9612c91e30ea541449957bc1a (patch) | |
tree | 171771f726cda0984411964545580600ddce518f /src/soc/mediatek | |
parent | 968292b8e14dea96bb3c222895788e0c7caf361b (diff) |
nb/i945/gma.c: correct VSYNC end offset
According to "G45: Volume 3: Display Register Intel ® 965G Express
Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the
VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
sets this register, which can be seen with intel-gpu-tools.
TESTED on Lenovo thinkpad X60 (it does not change anything).
Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17015
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/soc/mediatek')
0 files changed, 0 insertions, 0 deletions