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| author | Duncan Laurie <dlaurie@chromium.org> | 2015-12-10 01:01:59 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-18 12:09:37 +0100 |
| commit | ddd9f1a5a65db7a461ffb6576ca45acf56c2b000 (patch) | |
| tree | 58c44240e03ea6ea1d4d3328d07c8dec8f741080 /src/soc/mediatek | |
| parent | 63f8c0af4ba934f0a9eaefaed6ae411404962196 (diff) | |
intel/skylake: Add devicetree setting for DDR frequency limit UPD
There is a UPD setting exposed by FSP that allows the DDR
frequency to be limited. Expose this for devicetree.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=tested by limiting DDR frequency to 1600 on chell EVT
Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12981
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/mediatek')
0 files changed, 0 insertions, 0 deletions