diff options
| author | CK Hu <ck.hu@mediatek.com> | 2020-06-16 11:54:38 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-23 03:58:45 +0000 |
| commit | 3398f3152cf005d1e8219feacac1e1ec4fe50095 (patch) | |
| tree | a48952d88a85c011e4f401d4fd821c2e6d268a9e /src/soc/mediatek | |
| parent | 9190345bf071261a0764c9cfbe1472f974e2bd19 (diff) | |
soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/mmu_operations.c | 30 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/soc.c | 2 |
3 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index fb3b11de8c..8b2831cc6b 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c new file mode 100644 index 0000000000..fb3620eb82 --- /dev/null +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 9850fa6fbe..6978406cac 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev) static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { |