soc/mediatek/mt8196: Add NOR-Flash support

Add NOR-Flash drivers for flash read/write.

TEST=read nor flash data successfully.
BUG=b:317009620

Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83923
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 21 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c
index 11bbb5f143..09cd073f8a 100644
--- a/src/soc/mediatek/mt8196/spi.c
+++ b/src/soc/mediatek/mt8196/spi.c
@@ -6,16 +6,37 @@
  */
 
 #include <device/mmio.h>
+#include <gpio.h>
 #include <soc/addressmap.h>
+#include <soc/flash_controller_common.h>
 #include <soc/spi.h>
+#include <spi_flash.h>
+
+#define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel}
+
+static const struct mtk_snfc_pad_func nor_pinmux[4] = {
+	PAD_FUNC_SEL(SDA10, SF_CK, GPIO_PULL_DOWN),
+	PAD_FUNC_SEL(SCL10, SF_CS, GPIO_PULL_UP),
+	PAD_FUNC_SEL(PERIPHERAL_EN5, SF_D0, GPIO_PULL_DOWN),
+	PAD_FUNC_SEL(PERIPHERAL_EN6, SF_D1, GPIO_PULL_DOWN),
+};
+
+void mtk_snfc_init(void)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++)
+		mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_14_MA);
+}
 
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
 };
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 	{
 		.ctrlr = &spi_flash_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 	},
 };