diff options
| author | Liya Li <ot_liya.li@mediatek.corp-partner.google.com> | 2024-03-01 16:14:02 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-11-08 07:38:24 +0000 |
| commit | 4c96f14b3d3718a67f395942653be0a5844777e8 (patch) | |
| tree | 3ca898b9be3468e559650af8d38d79e7893ec492 /src/soc/mediatek/mt8196/include | |
| parent | 946b2556f90df6adc220edb006b4dc03f6440f28 (diff) | |
soc/mediatek/mt8196: Add SPI driver support
Add SPI controller driver code with support for 8 buses (SPI0 to SPI7).
Test=Build pass, verify the wavefroms for SPI0~7 are correct.
BUG=b:317009620
Change-Id: I10dd1105931c4911ce5257803073b7af76115c75
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8196/include')
| -rw-r--r-- | src/soc/mediatek/mt8196/include/soc/spi.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8196/include/soc/spi.h b/src/soc/mediatek/mt8196/include/soc/spi.h index 43edc89c52..2db20ab2aa 100644 --- a/src/soc/mediatek/mt8196/include/soc/spi.h +++ b/src/soc/mediatek/mt8196/include/soc/spi.h @@ -8,7 +8,21 @@ #ifndef SOC_MEDIATEK_MT8196_SPI_H #define SOC_MEDIATEK_MT8196_SPI_H -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 8 + +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg) + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16) +DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22) /* Initialize SPI NOR Flash Controller */ void mtk_snfc_init(void); |