diff options
| author | Yidi Lin <yidilin@chromium.org> | 2024-08-27 16:05:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-02 09:04:27 +0000 |
| commit | 62632ebf24cf50d77ab73e3458525561b77190da (patch) | |
| tree | d56acae34957ef167c4f242ecec55019654231b9 /src/soc/mediatek/mt8195 | |
| parent | 7c71b9498446ca45ac3b00af1c07eddfa5b89930 (diff) | |
soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195')
| -rw-r--r-- | src/soc/mediatek/mt8195/Makefile.mk | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/pcie.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/pcie.c | 23 |
3 files changed, 2 insertions, 24 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 344614499e..a37f715249 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -13,7 +13,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/early_init.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c -bootblock-$(CONFIG_PCI) += pcie.c +bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 117f4ccd3c..75c52c12c1 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -6,7 +6,6 @@ #include <soc/pcie_common.h> #include <types.h> -void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void); bool mainboard_needs_pcie_init(void); diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index eb7ad8725e..2676207db7 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -9,11 +9,6 @@ #include <soc/pcie_common.h> #define PCIE_REG_BASE_PORT0 0x112f0000 -#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) -#define PCIE_MAC_RSTB BIT(0) -#define PCIE_PHY_RSTB BIT(1) -#define PCIE_BRG_RSTB BIT(2) -#define PCIE_PE_RSTB BIT(3) struct pad_func { gpio_t gpio; @@ -46,28 +41,12 @@ static void mtk_pcie_set_pinmux(uint8_t port) } } -void mtk_pcie_reset(uintptr_t reg, bool enable) -{ - uint32_t val; - - val = read32p(reg); - - if (enable) - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - else - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - - write32p(reg, val); -} - void mtk_pcie_pre_init(void) { mtk_pcie_set_pinmux(0); /* Assert all reset signals at early stage */ - mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(PCIE_REG_BASE_PORT0, true); early_init_save_time(EARLY_INIT_PCIE); } |