soc/mediatek/mt8195: Add timer support

TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
     verified on Asurada and Cherry P0

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 36 insertions, 4 deletions

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 3fa1d1993d..302d2ff1ea 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -3,26 +3,26 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
 bootblock-y += bootblock.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-$(CONFIG_SPI_FLASH) += spi.c
-bootblock-y += ../common/timer.c
+bootblock-y += ../common/timer.c timer.c
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c
 
 verstage-$(CONFIG_SPI_FLASH) += spi.c
-verstage-y += ../common/timer.c
+verstage-y += ../common/timer.c timer.c
 verstage-y += ../common/uart.c
 verstage-y += ../common/wdt.c
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-$(CONFIG_SPI_FLASH) += spi.c
-romstage-y += ../common/timer.c
+romstage-y += ../common/timer.c timer.c
 romstage-y += ../common/uart.c
 romstage-y += ../common/wdt.c
 
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += soc.c
-ramstage-y += ../common/timer.c
+ramstage-y += ../common/timer.c timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/wdt.c
 
diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h
index 0f4bb8b450..417e2bd2c2 100644
--- a/src/soc/mediatek/mt8195/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h
@@ -22,6 +22,7 @@ enum {
 	GPT_BASE		= IO_PHYS + 0x00008000,
 	EINT_BASE		= IO_PHYS + 0x0000B000,
 	APMIXED_BASE		= IO_PHYS + 0x0000C000,
+	SYSTIMER_BASE		= IO_PHYS + 0x00017000,
 	PMIF_SPI_BASE	 	= IO_PHYS + 0x00024000,
 	PMICSPI_MST_BASE	= IO_PHYS + 0x00025000,
 	PMIF_SPMI_BASE		= IO_PHYS + 0x00027000,
diff --git a/src/soc/mediatek/mt8195/include/soc/timer.h b/src/soc/mediatek/mt8195/include/soc/timer.h
new file mode 100644
index 0000000000..da073e1b7a
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/timer.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_TIMER_H
+#define SOC_MEDIATEK_MT8195_TIMER_H
+
+#include <soc/timer_v2.h>
+
+enum {
+	TIE_0_EN = 1 << 3,
+	COMP_15_EN = 1 << 10,
+	COMP_20_EN = 1 << 11,
+	COMP_25_EN = 1 << 12,
+
+	COMP_FEATURE_MASK = COMP_15_EN | COMP_20_EN | COMP_25_EN | TIE_0_EN,
+
+	COMP_15_MASK = COMP_15_EN,
+	COMP_20_MASK = COMP_20_EN | TIE_0_EN,
+	COMP_25_MASK = COMP_20_EN | COMP_25_EN,
+};
+#endif
diff --git a/src/soc/mediatek/mt8195/timer.c b/src/soc/mediatek/mt8195/timer.c
new file mode 100644
index 0000000000..3fb4be7f2d
--- /dev/null
+++ b/src/soc/mediatek/mt8195/timer.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/timer.h>
+
+void timer_prepare(void)
+{
+	clrbits32((void *)SYSTIMER_BASE, COMP_FEATURE_MASK);
+	setbits32((void *)SYSTIMER_BASE, COMP_25_MASK);
+}