soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed

1. The original algorithm for I2C speed cannot always make the
   timing meet I2C specification so a new algorithm is introduced
   to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
   the original implementation was fixed at fast mode (400Khz).
   So the mtk_i2c_bus_init is now also taking an extra speed
   parameter.

There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1

BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
     at 100/300/400/500/800/1000Khz.

Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 240 insertions, 49 deletions

diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c
index 648083e7b6..960eb12a69 100644
--- a/src/soc/mediatek/mt8195/i2c.c
+++ b/src/soc/mediatek/mt8195/i2c.c
@@ -1,16 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <assert.h>
+#include <console/console.h>
 #include <device/mmio.h>
+#include <device/i2c_simple.h>
 #include <soc/pll.h>
 #include <soc/i2c.h>
 #include <soc/gpio.h>
+#include <timer.h>
 
 #define I2C_CLK_HZ (UNIVPLL_HZ / 20)
-#define I2C_FULL_DUTY 100
-#define I2C_HALF_DUTY 50
-#define I2C_ADJUSTED_DUTY 50
-#define I2C_FS_START_CON 0x0
 
 struct mtk_i2c mtk_i2c_bus_controller[] = {
 	[0] = {
@@ -112,57 +111,247 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
 	}
 }
 
-static void mtk_i2c_speed_init(uint8_t bus)
+static int mtk_i2c_max_step_cnt(uint32_t target_speed)
 {
-	uint8_t step_div;
-	const uint8_t clock_div = 5;
-	const uint8_t sample_div = 1;
-	uint32_t i2c_freq;
-	uint32_t tar_speed = 400;
-	uint32_t tar_speed_high;
-	uint32_t tar_speed_low;
+	if (target_speed > I2C_SPEED_FAST_PLUS)
+		return MAX_HS_STEP_CNT_DIV;
+	else
+		return MAX_STEP_CNT_DIV;
+}
 
-	assert(bus < I2C_BUS_NUMBER);
+/*
+ * Check and calculate i2c ac-timing.
+ *
+ * Hardware design:
+ * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
+ * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
+ *
+ * The calculation of sample_ns is rounded down;
+ * otherwise xxx_cnt_div would be greater than the smallest spec.
+ * The sda_timing is chosen as the middle value between
+ * the largest and smallest.
+ */
+static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
+				   uint32_t check_speed,
+				   uint32_t step_cnt,
+				   uint32_t sample_cnt)
+{
+	const struct i2c_spec_values *spec;
+	uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
+	uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
+	uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
+	struct mtk_i2c_ac_timing *ac_timing;
+
+	spec = mtk_i2c_get_spec(check_speed);
+
+	clk_ns = NSECS_PER_SEC / clk_src;
+
+	su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
+	if (su_sta_cnt > max_sta_cnt)
+		return -1;
+
+	low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
+	max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
+	if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
+		if (low_cnt > step_cnt) {
+			high_cnt = 2 * step_cnt - low_cnt;
+		} else {
+			high_cnt = step_cnt;
+			low_cnt = step_cnt;
+		}
+	} else {
+		return -2;
+	}
+
+	sda_max = spec->max_hd_dat_ns / sample_ns;
+	if (sda_max > low_cnt)
+		sda_max = 0;
+
+	sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
+	if (sda_min < low_cnt)
+		sda_min = 0;
+
+	if (sda_min > sda_max)
+		return -3;
+
+	ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
+	if (check_speed > I2C_SPEED_FAST_PLUS) {
+		ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
+		ac_timing->ltiming &= ~GENMASK(15, 9);
+		ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
+		ac_timing->ext &= ~GENMASK(7, 1);
+		ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
+	} else {
+		ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
+		ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
+		ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
+	}
+
+	return 0;
+}
+
+/*
+ * Calculate i2c port speed.
+ *
+ * Hardware design:
+ * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
+ * clock_div: fixed in hardware, but may be various in different SoCs
+ *
+ * To calculate sample_cnt and step_cnt, we pick the highest bus frequency
+ * that is still no larger than i2c->speed_hz.
+ */
+static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
+				   uint32_t target_speed,
+				   uint32_t *timing_step_cnt,
+				   uint32_t *timing_sample_cnt)
+{
+	uint32_t step_cnt;
+	uint32_t sample_cnt;
+	uint32_t max_step_cnt;
+	uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
+	uint32_t base_step_cnt;
+	uint32_t opt_div;
+	uint32_t best_mul;
+	uint32_t cnt_mul;
+	uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
+	int32_t clock_div_constraint = 0;
+	int success = 0;
+
+	if (target_speed > I2C_SPEED_HIGH)
+		target_speed = I2C_SPEED_HIGH;
+
+	max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
+	base_step_cnt = max_step_cnt;
+
+	/* Find the best combination */
+	opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
+	best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
+
+	/* Search for the best pair (sample_cnt, step_cnt) with
+	 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
+	 * 0 < step_cnt < max_step_cnt
+	 * sample_cnt * step_cnt >= opt_div
+	 * optimizing for sample_cnt * step_cnt being minimal
+	 */
+	for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
+		if (sample_cnt == 1) {
+			if (clk_div != 0)
+				clock_div_constraint = 1;
+			else
+				clock_div_constraint = 0;
+		} else {
+			if (clk_div > 1)
+				clock_div_constraint = 1;
+			else if (clk_div == 0)
+				clock_div_constraint = -1;
+			else
+				clock_div_constraint = 0;
+		}
+
+		step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
+		if (step_cnt > max_step_cnt)
+			continue;
+
+		cnt_mul = step_cnt * sample_cnt;
+		if (cnt_mul >= best_mul)
+			continue;
+
+		if (mtk_i2c_check_ac_timing(bus, clk_src,
+					    target_speed, step_cnt - 1,
+					    sample_cnt - 1))
+			continue;
 
-	/* Adjust ratio of high/low level */
-	tar_speed_high = tar_speed * I2C_HALF_DUTY / I2C_ADJUSTED_DUTY;
+		success = 1;
+		best_mul = cnt_mul;
+		base_sample_cnt = sample_cnt;
+		base_step_cnt = step_cnt;
+		if (best_mul == opt_div + clock_div_constraint)
+			break;
 
-	/* Calculate i2c frequency */
-	step_div = DIV_ROUND_UP(I2C_CLK_HZ,
-				(tar_speed_high * KHz * sample_div * 2) * clock_div);
-	i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
-	assert(sample_div < 8 && step_div < 64 &&
-	       i2c_freq <= tar_speed_high * KHz &&
-	       i2c_freq >= (tar_speed_high - 20) * KHz);
+	}
+
+	if (!success)
+		return -1;
+
+	sample_cnt = base_sample_cnt;
+	step_cnt = base_step_cnt;
+
+	if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
+	    target_speed)
+		return -1;
+
+	*timing_step_cnt = step_cnt - 1;
+	*timing_sample_cnt = sample_cnt - 1;
+
+	return 0;
+}
+
+static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
+{
+	uint32_t max_clk_div = MAX_CLOCK_DIV;
+	uint32_t clk_src, clk_div, step_cnt, sample_cnt;
+	uint32_t l_step_cnt, l_sample_cnt;
+	uint32_t timing_reg_value, ltiming_reg_value;
+	struct mtk_i2c *bus_ctrl;
+
+	if (bus >= I2C_BUS_NUMBER) {
+		printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
+		return;
+	}
+
+	bus_ctrl = &mtk_i2c_bus_controller[bus];
+
+	for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
+		clk_src = I2C_CLK_HZ / clk_div;
+		bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
+
+		if (speed > I2C_SPEED_FAST_PLUS) {
+			/* Set master code speed register */
+			if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
+						    &l_step_cnt, &l_sample_cnt))
+				continue;
+
+			timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
+
+			/* Set the high speed mode register */
+			if (mtk_i2c_calculate_speed(bus, clk_src, speed,
+						    &step_cnt, &sample_cnt))
+				continue;
+
+			ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt |
+					    (sample_cnt << 12) | (step_cnt << 9);
+			bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
+		} else {
+			if (mtk_i2c_calculate_speed(bus, clk_src, speed,
+						    &l_step_cnt, &l_sample_cnt))
+				continue;
+
+			timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
+
+			/* Disable the high speed transaction */
+			bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
+
+			ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt;
+		}
+
+		break;
+	}
+
+	if (clk_div > max_clk_div) {
+		printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
+		return;
+	}
 
 	/* Init i2c bus timing register */
-	write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing,
-		(sample_div - 1) << 8 | (step_div - 1));
-
-	/* Adjust ratio of high/low level */
-	tar_speed_low = tar_speed * I2C_HALF_DUTY /
-			(I2C_FULL_DUTY - I2C_ADJUSTED_DUTY);
-
-	/* Calculate i2c frequency */
-	step_div = DIV_ROUND_UP(I2C_CLK_HZ,
-				(tar_speed_low * KHz * sample_div * 2) * clock_div);
-	i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
-	assert(sample_div < 8 && step_div < 64 &&
-	       i2c_freq <= tar_speed_low * KHz &&
-	       i2c_freq >= (tar_speed_low - 20) * KHz);
-	write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming,
-		(sample_div - 1) << 6 | (step_div - 1));
-
-	/* Init i2c bus clock_div register */
-	write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div,
-		clock_div - 1);
-
-	/* Adjust tSU,STA/tHD,STA/tSU,STO */
-	write32(&mtk_i2c_bus_controller[bus].i2c_regs->ext_conf, I2C_FS_START_CON);
+	write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
+	write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming);
+	write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming);
+	write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs);
+	write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext);
 }
 
-void mtk_i2c_bus_init(uint8_t bus)
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
 {
-	mtk_i2c_speed_init(bus);
+	mtk_i2c_speed_init(bus, speed);
 	mtk_i2c_set_gpio_pinmux(bus);
 }
diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h
index 977106e482..743faa1e53 100644
--- a/src/soc/mediatek/mt8195/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8195/include/soc/i2c.h
@@ -22,7 +22,8 @@ struct mt_i2c_regs {
 	uint32_t hs;
 	uint32_t io_config;
 	uint32_t fifo_addr_clr;
-	uint32_t reserved0[2];
+	uint32_t data_timing;
+	uint32_t reserved0;
 	uint32_t transfer_aux_len;
 	uint32_t clock_div;
 	uint32_t time_out;
@@ -51,8 +52,9 @@ enum {
 	I2C7,
 };
 
+#define MAX_CLOCK_DIV	32
 check_member(mt_i2c_regs, multi_dma, 0xf8c);
 
-void mtk_i2c_bus_init(uint8_t bus);
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
 
 #endif /* SOC_MEDIATEK_MT8195_I2C_H */