diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-21 12:52:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-26 10:05:22 +0000 |
| commit | f371a78d907666afde4d945a56f9ca1e9c2152c8 (patch) | |
| tree | 9dc7ab56424a3152f972cd0c208b90819e875c30 /src/soc/mediatek/mt8195 | |
| parent | d22cdbe73fb06e4fbb56884f83fcf27cca14e7e1 (diff) | |
soc/medaitek/mt8195: adjust USB phy shift value
There is a design issue of bit shift which will drop a bit for
USB3 phy on MT8195. Therefore, we add this patch to set USB phy
registers from value of efuse.
BUG=b:211528577
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com>
Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/usb.h | 17 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/usb.c | 28 |
2 files changed, 44 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/usb.h b/src/soc/mediatek/mt8195/include/soc/usb.h index e39ec3841d..c3b3c586f6 100644 --- a/src/soc/mediatek/mt8195/include/soc/usb.h +++ b/src/soc/mediatek/mt8195/include/soc/usb.h @@ -19,6 +19,21 @@ check_member(ssusb_sif_port, u3phya, 0x800); check_member(ssusb_sif_port, u3phya_da, 0x900); check_member(ssusb_sif_port, reserved2, 0xa00); -#define USB_PORT_NUMBER 1 +DEFINE_BIT(AUTO_LOAD_DIS, 12) +DEFINE_BITFIELD(TX_IMP_CAL, 28, 24) +DEFINE_BIT(TX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(RX_IMP_CAL, 28, 24) +DEFINE_BIT(RX_IMP_CAL_EN, 31) +DEFINE_BITFIELD(INTR_CAL, 15, 10) + +#define TX_IMP_MASK 0x1F +#define TX_IMP_SHIFT 0 +#define RX_IMP_MASK 0x3E0 +#define RX_IMP_SHIFT 5 +#define INTR_CAL_MASK 0xFC00 +#define INTR_CAL_SHIFT 10 + +#define USB_PHY_SETTING_REG 0x11C10184 +#define USB_PORT_NUMBER 1 #endif diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 7b6347e605..b3f00a97cc 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -10,3 +10,31 @@ void mtk_usb_prepare(void) setbits32(&mtk_topckgen->clk_cfg_11_clr, BIT(7) | BIT(15)); setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(1) | BIT(31)); } + +void mtk_usb_adjust_phy_shift(void) +{ + u32 phy_set_val, write_val; + struct ssusb_sif_port *phy = (void *)(SSUSB_SIF_BASE); + + SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, + AUTO_LOAD_DIS, 1); + + phy_set_val = read32((void *)USB_PHY_SETTING_REG); + + /* TX imp */ + write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal0, + TX_IMP_CAL, write_val, + TX_IMP_CAL_EN, 1); + + /* RX imp */ + write_val = (phy_set_val & RX_IMP_MASK) >> RX_IMP_SHIFT; + SET32_BITFIELDS(&phy->u3phyd.phyd_cal1, + RX_IMP_CAL, write_val, + RX_IMP_CAL_EN, 1); + + /* Intr_cal */ + write_val = (phy_set_val & INTR_CAL_MASK) >> INTR_CAL_SHIFT; + SET32_BITFIELDS(&phy->u3phya.phya_reg0, + INTR_CAL, write_val); +} |