soc/mediatek: Add chip config for setting PCIe config

Add chip config for setting PCIe config.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

4 files changed, 24 insertions, 27 deletions

diff --git a/src/soc/mediatek/mt8195/chip.h b/src/soc/mediatek/mt8195/chip.h
new file mode 100644
index 0000000000..7cc4d19141
--- /dev/null
+++ b/src/soc/mediatek/mt8195/chip.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_CHIP_H
+#define SOC_MEDIATEK_CHIP_H
+
+#include <soc/pcie_common.h>
+
+struct soc_mediatek_mt8195_config {
+	struct mtk_pcie_config pcie_config;
+};
+
+typedef struct soc_mediatek_mt8195_config mtk_soc_config_t;
+
+#endif /* SOC_MEDIATEK_CHIP_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h
index 0978531645..21a66681e4 100644
--- a/src/soc/mediatek/mt8195/include/soc/pcie.h
+++ b/src/soc/mediatek/mt8195/include/soc/pcie.h
@@ -5,7 +5,7 @@
 
 #include <soc/pcie_common.h>
 
+void mtk_pcie_reset(uintptr_t reg, bool enable);
 void mtk_pcie_pre_init(void);
-void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl);
 
 #endif
diff --git a/src/soc/mediatek/mt8195/include/soc/soc_chip.h b/src/soc/mediatek/mt8195/include/soc/soc_chip.h
new file mode 100644
index 0000000000..6b3c354445
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/soc_chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_SOC_CHIP_H
+#define SOC_MEDIATEK_SOC_CHIP_H
+
+#include "../../chip.h"
+
+#endif /* SOC_MEDIATEK_SOC_CHIP_H */
diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c
index 8a1fca479b..1a17c6c459 100644
--- a/src/soc/mediatek/mt8195/pcie.c
+++ b/src/soc/mediatek/mt8195/pcie.c
@@ -19,23 +19,6 @@
 #define PCIE_BRG_RSTB		BIT(2)
 #define PCIE_PE_RSTB		BIT(3)
 
-
-/* MMIO range (64MB): 0x20000000 ~ 0x24000000 */
-/* Some devices still need io ranges, reserve 16MB for compatibility */
-static const struct mtk_pcie_mmio_res pcie_mmio_res_io = {
-	.cpu_addr = 0x20000000,
-	.pci_addr = 0x20000000,
-	.size = 16 * MiB,
-	.type = IORESOURCE_IO,
-};
-
-static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = {
-	.cpu_addr = 0x21000000,
-	.pci_addr = 0x21000000,
-	.size = 48 * MiB,
-	.type = IORESOURCE_MEM,
-};
-
 struct pad_func {
 	gpio_t gpio;
 	u8 func;
@@ -67,7 +50,7 @@ static void mtk_pcie_set_pinmux(uint8_t port)
 	}
 }
 
-static void mtk_pcie_reset(uintptr_t reg, bool enable)
+void mtk_pcie_reset(uintptr_t reg, bool enable)
 {
 	uint32_t val;
 
@@ -90,11 +73,3 @@ void mtk_pcie_pre_init(void)
 	/* Assert all reset signals at early stage */
 	mtk_pcie_reset(PCIE_RST_CTRL_REG, true);
 }
-
-void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl)
-{
-	ctrl->base = PCIE_REG_BASE_PORT0;
-	ctrl->mmio_res_io = &pcie_mmio_res_io;
-	ctrl->mmio_res_mem = &pcie_mmio_res_mem;
-	ctrl->reset = &mtk_pcie_reset;
-}