diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-05-26 10:39:57 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:25:43 +0000 |
| commit | ba638c49c9ca7d96f63980cfce41d5482d055183 (patch) | |
| tree | 43f21c27e73c2c9c74c885ab6630659780a2b2d7 /src/soc/mediatek/mt8195 | |
| parent | 11e2e36c06cb2c443366fe3c31193b011a161251 (diff) | |
soc/mediatek/mt8195: Enable thermal hardware reset
Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.
Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.
This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.
This setting is based on thermal and watchdog section of MT8195
Function Specification.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia6489bb953d148a43af173454d6f2b3e2a1dfcf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64675
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195')
| -rw-r--r-- | src/soc/mediatek/mt8195/wdt.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/wdt.c b/src/soc/mediatek/mt8195/wdt.c index fcee3db21a..54038c98aa 100644 --- a/src/soc/mediatek/mt8195/wdt.c +++ b/src/soc/mediatek/mt8195/wdt.c @@ -5,6 +5,23 @@ #include <soc/wdt.h> #define MTK_WDT_CLR_STATUS 0x230001FF +#define MTK_WDT_REQ_MOD_KEY_VAL 0x33 +#define MTK_WDT_REQ_IRQ_KEY_VAL 0x44 + +DEFINE_BITFIELD(MTK_WDT_REQ_MOD_KEY, 31, 24) +DEFINE_BITFIELD(MTK_WDT_REQ_IRQ_KEY, 31, 24) +DEFINE_BIT(MTK_WDT_THERMAL_EN, 18) +DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 18) + +void mtk_wdt_preinit(void) +{ + SET32_BITFIELDS(&mtk_wdt->wdt_req_mode, + MTK_WDT_THERMAL_EN, 1, + MTK_WDT_REQ_MOD_KEY, MTK_WDT_REQ_MOD_KEY_VAL); + SET32_BITFIELDS(&mtk_wdt->wdt_req_irq_en, + MTK_WDT_THERMAL_IRQ, 0, + MTK_WDT_REQ_IRQ_KEY, MTK_WDT_REQ_IRQ_KEY_VAL); +} void mtk_wdt_clr_status(void) { |