diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-10-18 18:59:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-21 14:57:09 +0000 |
| commit | a6cd1bd6a89cb92bb0cc0a6cdae4d912644974de (patch) | |
| tree | aab8bf18b2523e1ab9b9d46923782c35fe651f22 /src/soc/mediatek/mt8195/pll.c | |
| parent | 08248c0ce8b270d8ace174e7e2767254c3c2a9ea (diff) | |
soc/mediatek: Unify PLL function names
For consistency with the PLL function naming:
- Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel().
- Rename mux_set_sel() to pll_mux_set_sel().
BUG=none
TEST=build pass.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/pll.c')
| -rw-r--r-- | src/soc/mediatek/mt8195/pll.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 06b2156702..792af7f360 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -755,7 +755,7 @@ void mt_pll_init(void) * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* switch sram control to bypass mode for PCIE_MAC_P0 */ setbits32(&mtk_spm->ap_mdsrc_req, 0x1); @@ -827,9 +827,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq) udelay(PLL_EN_DELAY); } -void edp_mux_set_sel(u32 sel) +void mt_pll_edp_mux_set_sel(u32 sel) { - mux_set_sel(&muxes[TOP_EDP_SEL], sel); + pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel); } u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) |