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authorPatrick Rudolph <patrick.rudolph@9elements.com>2024-10-24 13:12:14 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-19 10:35:34 +0000
commitdd46eb3c7c90063f652875036ea4cc50004a18f3 (patch)
treebbc04ce65e2671577eded1ba851b302bb1b22d0c /src/soc/mediatek/mt8195/pll.c
parent488e7bd9e4f964d80cd18c4ffa30e234a70982ce (diff)
soc/intel/xeon_sp: Read IOAPIC ID from hardware
Currently coreboot hardcodes the same IOAPIC IDs as used on UEFI native, however FSP does not program the IOAPIC IDs, except for PCH IOAPIC. Drop existing code that hardcodes PCI addresses and IOAPIC IDs and detect the IOAPIC inside the domain automatically, read the IOAPIC base address and let existing code figure out the IOAPIC ID by reading it back from HW. Change-Id: I2543a46dcc4a98ec8629530ca87882a7106c9ed1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84850 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/pll.c')
0 files changed, 0 insertions, 0 deletions