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| author | Martin Roth <martinroth@chromium.org> | 2021-06-15 11:19:57 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-06-22 21:30:05 +0000 |
| commit | 0a5837e9f192cde66d6e7d1e2818d6526c766d0a (patch) | |
| tree | 3ae66dd572691029c826672c8df830ad16752923 /src/soc/mediatek/mt8195/mt6360.c | |
| parent | 1687c243f5fa4a3bd473c08ca846e0740f11643a (diff) | |
soc/amd/common: Add GPIO config for native func w/ output drive
Our existing native function gpio configuration macro (PAD_NF) only sets
the pull. For PCIe reset, we now need to be able to set it to its
native function (PCIE_RST_L), and drive it low, then high.
BUG=b:182805349
TEST=Configure GPIO, see correct behavior.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I636371517c99f94f76834abc4575795d51aa0368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/mt6360.c')
0 files changed, 0 insertions, 0 deletions