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authorQii Wang <qii.wang@mediatek.com>2021-02-05 10:32:25 +0800
committerHung-Te Lin <hungte@chromium.org>2021-05-05 07:36:57 +0000
commitf46e2caebec91d83bd729e6812e51ca960a24f38 (patch)
tree07e3835379ed0b5e8c922a7b32d94393a009ded8 /src/soc/mediatek/mt8195/include
parent47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed (diff)
soc/mediatek/mt8195: Add SPI driver support
Add SPI controller driver code. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Change-Id: I674763cdb0f338e123c121ede52278cfe96df091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/include')
-rw-r--r--src/soc/mediatek/mt8195/include/soc/pll.h2
-rw-r--r--src/soc/mediatek/mt8195/include/soc/spi.h17
2 files changed, 18 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h
index 6d836f7e8f..60fcbd9884 100644
--- a/src/soc/mediatek/mt8195/include/soc/pll.h
+++ b/src/soc/mediatek/mt8195/include/soc/pll.h
@@ -562,10 +562,12 @@ enum {
/* top_div rate */
enum {
CLK26M_HZ = 26 * MHz,
+ UNIVPLL_D6_D2_HZ = UNIVPLL_HZ / 6 / 2,
};
/* top_mux rate */
enum {
+ SPI_HZ = UNIVPLL_D6_D2_HZ,
UART_HZ = CLK26M_HZ,
};
diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h
index cfa4f43a13..a74ed56439 100644
--- a/src/soc/mediatek/mt8195/include/soc/spi.h
+++ b/src/soc/mediatek/mt8195/include/soc/spi.h
@@ -3,6 +3,21 @@
#ifndef MTK_MT8195_SPI_H
#define MTK_MT8195_SPI_H
-#include <spi-generic.h>
+#include <soc/spi_common.h>
+
+#define SPI_BUS_NUMBER 6
+
+#define GET_SCK_REG(x) x->spi_cfg2_reg
+
+DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
+DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
+
+DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
+DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
+DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
#endif