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authorJarried Lin <jarried.lin@mediatek.corp-partner.google.com>2024-08-16 10:24:18 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-08-24 12:59:31 +0000
commitabf34584dbfecdd74db36dd24f6008d1051a96a9 (patch)
treeea87f2c2975420f01a877434c8cd8a268994d648 /src/soc/mediatek/mt8195/Makefile.mk
parent228088ea5276ad6dbcd7b145c89afb7aa6b8b203 (diff)
soc/mediatek: Refactor MMU operation for L2C SRAM and DMA
Refactor mmu operation by - moving mtk_soc_disable_l2c_sram to l2c_ops.c - keeping mtk_soc_after_dram in mmu_cmops.c Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/Makefile.mk')
-rw-r--r--src/soc/mediatek/mt8195/Makefile.mk2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk
index f91372aeb9..344614499e 100644
--- a/src/soc/mediatek/mt8195/Makefile.mk
+++ b/src/soc/mediatek/mt8195/Makefile.mk
@@ -23,6 +23,7 @@ romstage-y += ../common/clkbuf.c
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
romstage-y += emi.c
+romstage-y += ../common/l2c_ops.c
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
@@ -51,6 +52,7 @@ ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
ramstage-y += emi.c
ramstage-y += hdmi.c
+ramstage-y += ../common/l2c_ops.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c