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authorWeiyi Lu <weiyi.lu@mediatek.com>2020-07-23 15:04:48 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 09:21:39 +0000
commit8dfeb06eb139889a7bb71284897811cd37ce3d89 (patch)
tree407475fd1f849b57a28b899f4d4253c295e31c4a /src/soc/mediatek/mt8192
parente9fed766df9ebc6b9e0806d42be9a343f26f5011 (diff)
soc/mediatek/mt8192: Add function to raise the CCI frequency
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192')
-rw-r--r--src/soc/mediatek/mt8192/pll.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c
index 6d61fb4d5a..f0a9509173 100644
--- a/src/soc/mediatek/mt8192/pll.c
+++ b/src/soc/mediatek/mt8192/pll.c
@@ -559,3 +559,28 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
return 0;
}
+
+void mt_pll_raise_cci_freq(u32 freq)
+{
+ /* enable [4] intermediate clock armpll_divider_pll1_ck */
+ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+ /* switch cci clock source to intermediate clock */
+ clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_DIV_PLL1);
+
+ /* disable ccipll frequency output */
+ clrbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+
+ /* raise ccipll frequency */
+ pll_set_rate(&plls[APMIXED_CCIPLL], freq);
+
+ /* enable ccipll frequency output */
+ setbits32(plls[APMIXED_CCIPLL].reg, PLL_EN);
+ udelay(PLL_EN_DELAY);
+
+ /* switch cci clock source back to ccipll */
+ clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
+
+ /* disable [4] intermediate clock armpll_divider_pll1_ck */
+ clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+}