diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2020-11-11 10:44:15 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 11:04:11 +0000 |
| commit | 7de8df467aca97208f8cd5ff4e520d18f088378e (patch) | |
| tree | 826ea91465f376fca577b8fe250b585400951623 /src/soc/mediatek/mt8192 | |
| parent | 93538c99691b962fc69082b1d26e57911f76dc9c (diff) | |
soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working buffer
Reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K and reserve
0x00115000 ~ 0x0011ffff for MCUPM.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/memlayout.ld | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index df9d376f27..57b258c32c 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -21,11 +21,16 @@ SECTIONS TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) - TIMESTAMP(0x00113c00, 1K) - STACK(0x00114000, 16K) - TTB(0x00118000, 28K) - DMA_COHERENT(0x0011f000, 4K) + PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4) + TIMESTAMP(0x00108c00, 1K) + STACK(0x00109000, 16K) + TTB(0x0010d000, 28K) + DMA_COHERENT(0x00114000, 4K) + /* + * MCUPM exchanges data with kernel driver using SRAM 0x00115000 ~ 0x0011ffff. + * The address is hardcoded in MCUPM image and is unlikely to change. + */ + REGION(mcufw_reserved, 0x00115000, 44K, 4K) SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) |