soc/mediatek/mt8195: add pmif/spmi/pmic driver

MT8195 also uses mt6359p so we can reuse most drivers.
The only differences are IO configuaration, clock setting, and PMIC
internal setting related to soc.

Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.

Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

2 files changed, 3 insertions, 43 deletions

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 865ff40b9d..e2abc5ef25 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -35,7 +35,7 @@ romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c
 romstage-y += ../common/uart.c
-romstage-y += ../common/pmif.c pmif_clk.c
+romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
 romstage-y += ../common/pmif_spi.c pmif_spi.c
 romstage-y += ../common/pmif_spmi.c pmif_spmi.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c
index a597b6a724..e5c0d1daf5 100644
--- a/src/soc/mediatek/mt8192/pmif_clk.c
+++ b/src/soc/mediatek/mt8192/pmif_clk.c
@@ -8,6 +8,7 @@
 #include <soc/pll.h>
 #include <soc/pll_common.h>
 #include <soc/pmif.h>
+#include <soc/pmif_clk_common.h>
 #include <soc/pmif_sw.h>
 #include <soc/pmif_spmi.h>
 #include <soc/spm.h>
@@ -72,7 +73,7 @@ static void pmif_ulposc_config(void)
 	SET32_BITFIELDS(&mtk_apmixed->ulposc1_con2, OSC1_BIAS, 0x40);
 }
 
-static u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
+u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
 {
 	u32 result = 0;
 
@@ -84,47 +85,6 @@ static u32 pmif_get_ulposc_freq_mhz(u32 cali_val)
 	return result / 1000;
 }
 
-static int pmif_ulposc_cali(u32 target_val)
-{
-	u32 current_val = 0, min = 0, max = CAL_MAX_VAL, middle;
-	int ret = 0, diff_by_min, diff_by_max, cal_result;
-
-	do {
-		middle = (min + max) / 2;
-		if (middle == min)
-			break;
-
-		current_val = pmif_get_ulposc_freq_mhz(middle);
-		if (current_val > target_val)
-			max = middle;
-		else
-			min = middle;
-	} while (min <= max);
-
-	diff_by_min = pmif_get_ulposc_freq_mhz(min) - target_val;
-	diff_by_min = ABS(diff_by_min);
-
-	diff_by_max = pmif_get_ulposc_freq_mhz(max) - target_val;
-	diff_by_max = ABS(diff_by_max);
-
-	if (diff_by_min < diff_by_max) {
-		cal_result = min;
-		current_val = pmif_get_ulposc_freq_mhz(min);
-	} else {
-		cal_result = max;
-		current_val = pmif_get_ulposc_freq_mhz(max);
-	}
-
-	/* check if calibrated value is in the range of target value +- 15% */
-	if (current_val < (target_val * (1000 - CAL_TOL_RATE) / 1000) ||
-		current_val > (target_val * (1000 + CAL_TOL_RATE) / 1000)) {
-		printk(BIOS_ERR, "[%s] calibration fail: %dM\n", __func__, current_val);
-		ret = 1;
-	}
-
-	return ret;
-}
-
 static int pmif_init_ulposc(void)
 {
 	/* calibrate ULPOSC1 */