diff options
| author | Sen Chu <sen.chu@mediatek.corp-partner.google.com> | 2022-10-18 13:41:09 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-21 14:53:53 +0000 |
| commit | 28dceaec717111ae49383ecc8678bcef424cda14 (patch) | |
| tree | 443db6efb02ef7803447536f26f4f1f83f5def44 /src/soc/mediatek/mt8192 | |
| parent | 1543252e5fcc0de821a5f6de38b10ed31b0cb920 (diff) | |
soc/mediatek: Move SPMI interface configuration to SoC folder
The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
fix this.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192')
| -rw-r--r-- | src/soc/mediatek/mt8192/pmif_spmi.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c index 1862af5408..d2155fadef 100644 --- a/src/soc/mediatek/mt8192/pmif_spmi.c +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -56,6 +56,27 @@ int spmi_config_master(void) return 0; } +void pmif_spmi_config(struct pmif *arb, int mstid) +{ + u32 cmd_per; + + /* Clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* Enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); +} + void pmif_spmi_iocfg(void) { SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2); |