diff options
| author | Ashish Kumar Mishra <ashish.k.mishra@intel.com> | 2024-01-16 16:23:03 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-08 13:02:34 +0000 |
| commit | ecbc243a45de3b7894e2fe6c8e22b5d07172274b (patch) | |
| tree | 6fffd581ee5293c58d5a48723ecc7b08c564bc6a /src/soc/mediatek/mt8192/spi.c | |
| parent | 32ebaef73c8e1cc367e1c63af587250041fce32a (diff) | |
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80088
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/mediatek/mt8192/spi.c')
0 files changed, 0 insertions, 0 deletions