soc/mediatek: rtc: Use `bool` as return type

BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 11 insertions, 11 deletions

diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c
index 86158731a8..d966cabb59 100644
--- a/src/soc/mediatek/mt8192/rtc.c
+++ b/src/soc/mediatek/mt8192/rtc.c
@@ -41,11 +41,11 @@ static void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift)
 }
 
 /* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
 	if (!rtc_writeif_unlock()) {
 		rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
 	}
 
 	u16 bbpu, con, osc32con, sec;
@@ -58,18 +58,18 @@ static int rtc_enable_dcxo(void)
 
 	if (!rtc_xosc_write(osc32con)) {
 		rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
 	}
 
 	rtc_read(RTC_CON, &con);
 	rtc_read(RTC_OSC32CON, &osc32con);
 	rtc_read(RTC_AL_SEC, &sec);
 	rtc_info("con=%#x, osc32con=%#x, sec=%#x\n", con, osc32con, sec);
-	return 1;
+	return true;
 }
 
 /* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
 	u16 con;
 
@@ -134,7 +134,7 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 		rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
 		if (stopwatch_expired(&sw)) {
 			rtc_info("get frequency time out!\n");
-			return 0;
+			return false;
 		}
 	} while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
 
@@ -162,7 +162,7 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 }
 
 /* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
 	u16 con, sec;
 
@@ -172,26 +172,26 @@ static int rtc_lpd_init(void)
 	rtc_write(RTC_AL_SEC, sec);
 
 	if (!rtc_write_trigger())
-		return 0;
+		return false;
 
 	/* init XOSC32 to detect 32k clock stop */
 	rtc_read(RTC_CON, &con);
 	con |= RTC_CON_XOSC32_LPEN;
 
 	if (!rtc_lpen(con))
-		return 0;
+		return false;
 
 	/* init EOSC32 to detect rtc low power */
 	rtc_read(RTC_CON, &con);
 	con |= RTC_CON_EOSC32_LPEN;
 
 	if (!rtc_lpen(con))
-		return 0;
+		return false;
 
 	rtc_read(RTC_CON, &con);
 	rtc_info("check RTC_CON_LPSTA_RAW after LP init: %#x\n", con);
 
-	return 1;
+	return true;
 }
 
 static bool rtc_hw_init(void)