diff options
author | Yidi Lin <yidi.lin@mediatek.com> | 2020-11-06 17:52:56 +0800 |
---|---|---|
committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-20 08:40:58 +0000 |
commit | 2832d11dd1aa59a195c67296a2a39ae4689b74eb (patch) | |
tree | 110d90fb62790cc16f05d26367459490589d9114 /src/soc/mediatek/mt8192/mmu_operations.c | |
parent | f06dd678e6bc916d29335b945f54d732b31e1ee2 (diff) |
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.
TEST=verified with SPM WIP patch.
SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/mmu_operations.c')
-rw-r--r-- | src/soc/mediatek/mt8192/mmu_operations.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620eb82..e3bc62282d 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h> DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void) MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} |