soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c
new file mode 100644
index 0000000000..fb3620eb82
--- /dev/null
+++ b/src/soc/mediatek/mt8192/mmu_operations.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}