soc/mediatek/common: Move DRAM implementation from mt8192 to common

To reduce duplicated dram sources on seperate SOCs,
add dpm, dram_init, dramc_params, memory(fast-k or full-k)
implementations, also add dramc log level macro header files.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

5 files changed, 47 insertions, 237 deletions

diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h
deleted file mode 100644
index f5e704bc10..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dpm.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DPM_H__
-#define __SOC_MEDIATEK_MT8192_DPM_H__
-
-#include <soc/addressmap.h>
-#include <stdint.h>
-#include <types.h>
-
-struct dpm_regs {
-	u32 sw_rstn;
-	u32 rsvd_0[3072];
-	u32 mclk_div;
-	u32 rsvd_1[3071];
-	u32 twam_window_len;
-	u32 twam_mon_type;
-	u32 rsvd_2[1022];
-	u32 low_power_cfg_0;
-	u32 low_power_cfg_1;
-	u32 rsvd_3[1];
-	u32 fsm_out_ctrl_0;
-	u32 rsvd_4[8];
-	u32 fsm_cfg_1;
-	u32 low_power_cfg_3;
-	u32 dfd_dbug_0;
-	u32 rsvd_5[28];
-	u32 status_4;
-};
-
-check_member(dpm_regs, mclk_div, 0x3004);
-check_member(dpm_regs, twam_window_len, 0x6004);
-check_member(dpm_regs, low_power_cfg_0, 0x7004);
-check_member(dpm_regs, low_power_cfg_1, 0x7008);
-check_member(dpm_regs, fsm_out_ctrl_0, 0x7010);
-check_member(dpm_regs, fsm_cfg_1, 0x7034);
-check_member(dpm_regs, low_power_cfg_3, 0x7038);
-check_member(dpm_regs, dfd_dbug_0, 0x703C);
-check_member(dpm_regs, status_4, 0x70B0);
-
-#define DPM_SW_RSTN_RESET	BIT(0)
-#define DPM_MEM_RATIO_OFFSET	28
-#define DPM_MEM_RATIO_MASK	(0x3 << DPM_MEM_RATIO_OFFSET)
-#define DPM_MEM_RATIO_CFG1	(1 << DPM_MEM_RATIO_OFFSET)
-
-static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE;
-
-int dpm_init(void);
-
-#endif  /* __SOC_MEDIATEK_MT8192_DPM_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h b/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
index 185ba8d6bd..b5c7889803 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
@@ -4,18 +4,6 @@
 #define __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__
 
 enum {
-	CHANNEL_A = 0,
-	CHANNEL_B,
-	CHANNEL_MAX
-};
-
-enum {
-	RANK_0 = 0,
-	RANK_1,
-	RANK_MAX
-};
-
-enum {
 	FSP_0 = 0,
 	FSP_1,
 	FSP_MAX,
@@ -56,13 +44,6 @@ enum {
 	DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER),
 };
 #define BYTE_NUM		DQS_NUMBER
-#define DQS_NUMBER_LP4		DQS_NUMBER
-#define DQ_DATA_WIDTH_LP4	DQ_DATA_WIDTH
-
-typedef enum {
-	CBT_NORMAL_MODE = 0,
-	CBT_BYTE_MODE1
-} dram_cbt_mode;
 
 /* DONOT change the sequence of pinmux */
 typedef enum {
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
deleted file mode 100644
index b4e982fdff..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__
-#define __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__
-
-#include <stdint.h>
-#include <sys/types.h>
-#include <soc/dramc_common_mt8192.h>
-
-enum {
-	DRAMC_PARAM_HEADER_VERSION = 3,
-};
-
-enum DRAMC_PARAM_STATUS_CODES {
-	DRAMC_SUCCESS = 0,
-	DRAMC_ERR_INVALID_VERSION,
-	DRAMC_ERR_INVALID_SIZE,
-	DRAMC_ERR_INVALID_CHECKSUM,
-	DRAMC_ERR_INVALID_FLAGS,
-	DRAMC_ERR_RECALIBRATE,
-	DRAMC_ERR_INIT_DRAM,
-	DRAMC_ERR_COMPLEX_RW_MEM_TEST,
-	DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST,
-	DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST,
-	DRAMC_ERR_FAST_CALIBRATION,
-};
-
-enum DRAMC_PARAM_DVFS_FLAG {
-	DRAMC_DISABLE_DVFS,
-	DRAMC_ENABLE_DVFS,
-};
-
-enum DRAMC_PARAM_FLAGS {
-	DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
-};
-
-enum DRAMC_PARAM_DDR_TYPE {
-	DDR_TYPE_DISCRETE,
-	DDR_TYPE_EMCP,
-};
-
-enum DRAMC_PARAM_GEOMETRY_TYPE {
-	DDR_TYPE_2CH_2RK_4GB_2_2,
-	DDR_TYPE_2CH_2RK_6GB_3_3,
-	DDR_TYPE_2CH_2RK_8GB_4_4,
-	DDR_TYPE_2CH_1RK_4GB_4_0,
-	DDR_TYPE_2CH_2RK_6GB_2_4,
-};
-
-enum DRAM_PARAM_VOLTAGE_TYPE {
-	DRAM_VOLTAGE_NVCORE_NVDRAM,
-	DRAM_VOLTAGE_HVCORE_HVDRAM,
-	DRAM_VOLTAGE_LVCORE_LVDRAM,
-};
-
-struct dramc_param_header {
-	u32 checksum;	/* checksum of dramc_datas, update in the coreboot */
-	u16 version;	/* DRAMC_PARAM_HEADER_VERSION, update in the coreboot */
-	u16 size;	/* size of whole dramc_param, update in the coreboot */
-	u16 status;	/* DRAMC_PARAM_STATUS_CODES, update in the dram blob */
-	u16 flags;	/* DRAMC_PARAM_FLAGS, update in the dram blob */
-};
-
-struct sdram_params {
-	u32 rank_num;
-	u16 num_dlycell_perT;
-	u16 delay_cell_timex100;
-
-	/* duty */
-	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
-	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
-	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
-	s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
-	s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
-
-	/* CBT */
-	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
-	s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
-	u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
-	u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER];
-
-	/* write leveling */
-	u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-
-	/* Gating */
-	u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-
-	/* TX perbit */
-	u8 tx_window_vref[CHANNEL_MAX][RANK_MAX];
-	u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
-
-	/* rx datlat */
-	u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
-
-	/* RX perbit */
-	u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
-
-	/* TX OE */
-	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-};
-
-struct emi_mdl {
-	u32 cona_val;
-	u32 conh_val;
-	u32 conf_val;
-	u32 chn_cona_val;
-};
-
-struct ddr_base_info {
-	u16 config_dvfs;		/* DRAMC_PARAM_DVFS_FLAG */
-	u16 ddr_type;			/* DRAMC_PARAM_DDR_TYPE */
-	u16 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
-	u16 voltage_type;		/* DRAM_PARAM_VOLTAGE_TYPE */
-	u32 support_ranks;
-	u64 rank_size[RANK_MAX];
-	struct emi_mdl emi_config;
-	dram_cbt_mode cbt_mode[RANK_MAX];
-};
-
-struct dramc_data {
-	struct ddr_base_info ddr_info;
-	struct sdram_params freq_params[DRAM_DFS_SHU_MAX];
-};
-
-struct dramc_param {
-	struct dramc_param_header header;
-	void (*do_putc)(unsigned char c);
-	struct dramc_data dramc_datas;
-};
-
-struct dramc_param_ops {
-	struct dramc_param *param;
-	bool (*read_from_flash)(struct dramc_param *dparam);
-	bool (*write_to_flash)(const struct dramc_param *dparam);
-};
-
-struct sdram_info {
-	u32 ddr_geometry;		/* DRAMC_PARAM_GEOMETRY_TYPE */
-};
-
-const struct sdram_info *get_sdram_config(void);
-struct dramc_param *get_dramc_param_from_blob(void *blob);
-void dump_param_header(const void *blob);
-int validate_dramc_param(const void *blob);
-int is_valid_dramc_param(const void *blob);
-int initialize_dramc_param(void *blob);
-#endif  /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_soc.h b/src/soc/mediatek/mt8192/include/soc/dramc_soc.h
new file mode 100644
index 0000000000..1b90eb134e
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_soc.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_DRAMC_SOC_H__
+#define __SOC_MEDIATEK_DRAMC_SOC_H__
+
+typedef enum {
+	CHANNEL_A = 0,
+	CHANNEL_B,
+	CHANNEL_MAX
+} DRAM_CHANNEL_T;
+
+typedef enum {
+	RANK_0 = 0,
+	RANK_1,
+	RANK_MAX
+} DRAM_RANK_T;
+
+typedef enum {
+	DRAM_DFS_SHUFFLE_1 = 0,
+	DRAM_DFS_SHUFFLE_2,
+	DRAM_DFS_SHUFFLE_3,
+	DRAM_DFS_SHUFFLE_4,
+	DRAM_DFS_SHUFFLE_5,
+	DRAM_DFS_SHUFFLE_6,
+	DRAM_DFS_SHUFFLE_7,
+	DRAM_DFS_SHUFFLE_MAX
+} DRAM_DFS_SHUFFLE_TYPE_T; // DRAM SHUFFLE RG type
+
+/*
+ * Internal CBT mode enum
+ * 1. Calibration flow uses vGet_Dram_CBT_Mode to
+ *    differentiate between mixed vs non-mixed LP4
+ * 2. Declared as dram_cbt_mode[RANK_MAX] internally to
+ *    store each rank's CBT mode type
+ */
+typedef enum {
+	CBT_NORMAL_MODE = 0,
+	CBT_BYTE_MODE1
+} DRAM_CBT_MODE_T, dram_cbt_mode;
+
+#define DRAM_DFS_SHU_MAX	DRAM_DFS_SHUFFLE_MAX
+
+#define DQS_NUMBER_LP4              2
+#define DQS_BIT_NUMBER              8
+#define DQ_DATA_WIDTH_LP4           16
+
+#endif	/* __SOC_MEDIATEK_DRAMC_SOC_H__ */
diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h
deleted file mode 100644
index 02a90be789..0000000000
--- a/src/soc/mediatek/mt8192/include/soc/emi.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_MEDIATEK_MT8192_EMI_H
-#define SOC_MEDIATEK_MT8192_EMI_H
-
-#include <soc/dramc_param.h>
-
-size_t sdram_size(void);
-void mt_set_emi(const struct dramc_data *dparam);
-void mt_mem_init(struct dramc_param_ops *dparam_ops);
-int complex_mem_test(u8 *start, unsigned int len);
-
-#endif /* SOC_MEDIATEK_MT8192_EMI_H */