diff options
| author | Chien-Chih Tseng <chien-chih.tseng@mediatek.com> | 2020-12-14 14:59:39 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-11 08:51:09 +0000 |
| commit | a39ea90506ea200f3dbf2c14bea82c327a37edbc (patch) | |
| tree | 324c502e5a39a6a4984354442f874747f8cdf695 /src/soc/mediatek/mt8192/include | |
| parent | 0250a7888d91f816310fd5bd36c86d05167a7403 (diff) | |
soc/mediatek/mt8192: add apusys init flow
Setup APU mbox's functional configuration registers.
BUG=b:186369803
BRANCH=asurada
TEST=boot asurada correctly
Signed-off-by: Chien-Chih Tseng <chien-chih.tseng@mediatek.com>
Change-Id: If05a8af1a2f96598adcf70e15003e4f5dc94e337
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48622
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/apusys.h | 27 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 51a89e1cf3..8dd76d9df3 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -87,6 +87,7 @@ enum { DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000, DISP_DITHER0_BASE = IO_PHYS + 0x0400E000, DSI0_BASE = IO_PHYS + 0x04010000, + APU_MBOX_BASE = IO_PHYS + 0x09000000, }; #endif diff --git a/src/soc/mediatek/mt8192/include/soc/apusys.h b/src/soc/mediatek/mt8192/include/soc/apusys.h new file mode 100644 index 0000000000..9a7e92658f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/apusys.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_APUSYS_H +#define SOC_MEDIATEK_MT8192_APUSYS_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_apu_mbox_regs { + u32 mbox_in[8]; + u32 mbox_out[8]; + u32 mbox_reserved1[28]; + u32 mbox_func_cfg; + u32 mbox0_reserved2[19]; +}; + +check_member(mt8192_apu_mbox_regs, mbox_func_cfg, 0x0b0); + +static struct mt8192_apu_mbox_regs * const mt8192_apu_mbox[] = { + (void *)APU_MBOX_BASE, + (void *)(APU_MBOX_BASE + 0x100), + (void *)(APU_MBOX_BASE + 0x500), + (void *)(APU_MBOX_BASE + 0x600), +}; + +void apusys_init(void); +#endif /* SOC_MEDIATEK_MT8192_APUSYS_H */ |