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authorHuayang Duan <huayang.duan@mediatek.com>2020-06-23 14:14:33 +0800
committerHung-Te Lin <hungte@chromium.org>2020-12-31 03:07:16 +0000
commit4cb885e5be06bc07624a00d33ef4cc1966344255 (patch)
treede8c017479ce3512732d21c8cf78e279b0fe597b /src/soc/mediatek/mt8192/include
parentc6589aefc16dc8911bc07c2fbdf2e81efe732796 (diff)
soc/mediatek/mt8192: Update initial settings of dramc
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
-rw-r--r--src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
index a958d0cc15..5a2583cb7f 100644
--- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
@@ -337,7 +337,7 @@ void ana_clk_div_config(ana_dvfs_core *tr, dvfs_group_config *dfs);
void apply_write_dbi_power_improve(bool onoff);
void dramc_write_dbi_onoff(u8 onoff);
void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay);
-void dramc_cmd_UI_delay_setting(u8 chn, u8 value);
+void dramc_cmd_ui_delay_setting(u8 chn, u8 value);
void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali *cali,
u16 *osc_thrd_inc, u16 *osc_thrd_dec);
void dqsosc_shu_settings(const struct ddr_cali *cali,