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| author | Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com> | 2021-01-21 14:38:23 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-15 02:28:32 +0000 |
| commit | 31f914c5544ba4fd4f5a4b8cfc09a7657354adcc (patch) | |
| tree | 4329c8fb1c5aaae295302a05b4cf12a9f0f57dda /src/soc/mediatek/mt8192/include | |
| parent | a79d6e76b852e5e5a4667818722388f1a07497df (diff) | |
soc/mediatek/mt8192: devapc: Add domain remap setting
MT8192 devapc supports remapping domains.
There may be different domain bit for different subsys.
For example, domain bit in INFRA is 4-bit, while in MMSYS,
domain bit is 2-bit. For INFRA master to access MM registers,
the domain bit will change from 4 to 2 and need to be remapped.
In this patch we have remapped:
1. TINYSYS (3-bit to 4-bit)
- domain 3 to domain 3
- others to domain 15
2. MMSYS slave (4-bit to 2-bit)
- domain X to domain X, for X = 0 ~ 3
- others to domain 0
Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/devapc.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h index f227aaadd3..7ba6d46477 100644 --- a/src/soc/mediatek/mt8192/include/soc/devapc.h +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -11,6 +11,10 @@ void dapc_init(void); #define DEVAPC_AO_MAX 6 enum devapc_ao_offset { + DOM_REMAP_0_0 = 0x800, + DOM_REMAP_1_0 = 0x810, + DOM_REMAP_1_1 = 0x814, + DOM_REMAP_2_0 = 0x820, MAS_DOM_0 = 0x0900, MAS_DOM_1 = 0x0904, MAS_SEC_0 = 0x0A00, @@ -48,5 +52,19 @@ enum master_domain { MAS_DOMAIN_MAX, }; +/* Domain Remap */ +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_0, 3, 0) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_1, 7, 4) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_2, 11, 8) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_3, 15, 12) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_4, 19, 16) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_5, 23, 20) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_6, 27, 24) +DEFINE_BITFIELD(FOUR_BIT_DOM_REMAP_7, 31, 28) + +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_1, 3, 2) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_2, 5, 4) +DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_3, 7, 6) #endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ |