diff options
| author | Qii Wang <qii.wang@mediatek.com> | 2020-05-27 17:23:04 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-13 10:12:32 +0000 |
| commit | 160b3d7e9d118ff04a226b1dd2e7309f3bfd175e (patch) | |
| tree | 43b2ded3f6b8c7950a8dc6ef28ecf0ee719b5fa2 /src/soc/mediatek/mt8192/include | |
| parent | 053fe8a3b24c1a47be7ae7a87b03f400b0665d9f (diff) | |
soc/mediatek/mt8192: Add spi driver
Add driver for MT8192 SPI controller
TEST=Boots correctly on MT8192EVB
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/addressmap.h | 8 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/spi.h | 44 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index c4b30472cd..e0cd5364a3 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -23,6 +23,14 @@ enum { APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, UART0_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01018000, + SPI5_BASE = IO_PHYS + 0x01019000, + SPI6_BASE = IO_PHYS + 0x0101D000, + SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h new file mode 100644 index 0000000000..034fa3570a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MTK_MT8192_SPI_H +#define MTK_MT8192_SPI_H + +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 8 + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +enum { + SPI_CFG0_CS_HOLD_SHIFT = 0, + SPI_CFG0_CS_SETUP_SHIFT = 16, +}; + +enum { + SPI_CFG2_SCK_LOW_SHIFT = 0, + SPI_CFG2_SCK_HIGH_SHIFT = 16, +}; + +enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, +}; + +#endif |