diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-08-06 15:33:38 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-10 14:04:59 +0000 |
| commit | 916e2efad4daaf6572107ed2e9b669e434eb5629 (patch) | |
| tree | 6b3c2f6a79404534fd7ee00e413f8d46db124164 /src/soc/mediatek/mt8192/include | |
| parent | 344f68be108fca3b9fe8e4280ce8015f1dd8c8e1 (diff) | |
soc/mediatek/mt8192: Init DPM
DPM is a hardware module for DRAM power management and for better
power saving in low power mode.
BUG=none
TEST=Boots correctly on Asurada
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/addressmap.h | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/dpm.h | 49 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index c68403b2b5..2e8ac9e715 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -27,6 +27,9 @@ enum { PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h new file mode 100644 index 0000000000..f5e704bc10 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dpm.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DPM_H__ +#define __SOC_MEDIATEK_MT8192_DPM_H__ + +#include <soc/addressmap.h> +#include <stdint.h> +#include <types.h> + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0); + +#define DPM_SW_RSTN_RESET BIT(0) +#define DPM_MEM_RATIO_OFFSET 28 +#define DPM_MEM_RATIO_MASK (0x3 << DPM_MEM_RATIO_OFFSET) +#define DPM_MEM_RATIO_CFG1 (1 << DPM_MEM_RATIO_OFFSET) + +static struct dpm_regs *const mtk_dpm = (void *)DPM_CFG_BASE; + +int dpm_init(void); + +#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */ |