soc/mediatek/mt8192: Do dramc pre-settings before calibration

Before calibration, dramc resets the delay of each PHY IO, calculates
TX path and sets CKE to be rank independent.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c
index 893913b360..80ee9edcc4 100644
--- a/src/soc/mediatek/mt8192/emi.c
+++ b/src/soc/mediatek/mt8192/emi.c
@@ -314,6 +314,17 @@ void emi_mdl_init(const struct emi_mdl *emi_con)
 		write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val);
 }
 
+u32 get_column_num(void)
+{
+	u32 ma_type = read32(&emi_reg->cona);
+	u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1;
+	u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1;
+
+	ma_type = MIN(ma_type_r0, ma_type_r1);
+
+	return ma_type;
+}
+
 static void emi_sw_setting(void)
 {
 	setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));