soc/mediatek/mt8192: devapc: Add domain remap setting

MT8192 devapc supports remapping domains.
There may be different domain bit for different subsys.
For example, domain bit in INFRA is 4-bit, while in MMSYS,
domain bit is 2-bit. For INFRA master to access MM registers,
the domain bit will change from 4 to 2 and need to be remapped.

In this patch we have remapped:

1. TINYSYS (3-bit to 4-bit)
   - domain 3 to domain 3
   - others to domain 15

2. MMSYS slave (4-bit to 2-bit)
   - domain X to domain X, for X = 0 ~ 3
   - others to domain 0

Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 58 insertions, 14 deletions

diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c
index d297d523b1..9e3692e634 100644
--- a/src/soc/mediatek/mt8192/devapc.c
+++ b/src/soc/mediatek/mt8192/devapc.c
@@ -16,6 +16,33 @@ static void infra_master_init(uintptr_t base)
 	SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1);
 	SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2,
 			CPU_EB_DOM, MAS_DOMAIN_2);
+
+	/*
+	 * Domain Remap: TINYSYS to non-EMI (3-bit to 4-bit)
+	 *    1. SCP from 3 to 3
+	 *    2. others from XXX to 15
+	 */
+	SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0),
+			FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3,
+			FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15);
+
+	/*
+	 * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit)
+	 *    1. From domain 0 ~ 3 to domain 0 ~ 3
+	 *    2. others from XXX to domain 0
+	 */
+	SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0),
+			TWO_BIT_DOM_REMAP_0, MAS_DOMAIN_0,
+			TWO_BIT_DOM_REMAP_1, MAS_DOMAIN_1,
+			TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_2,
+			TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3);
+
 }
 
 static void peri_master_init(uintptr_t base)
@@ -24,33 +51,50 @@ static void peri_master_init(uintptr_t base)
 	SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2);
 }
 
-static uintptr_t devapc_base[DEVAPC_AO_MAX] = {
-	DEVAPC_INFRA_AO_BASE,
-	DEVAPC_PERI_AO_BASE,
-	DEVAPC_PERI2_AO_BASE,
-	DEVAPC_PERI_PAR_AO_BASE,
-	DEVAPC_FMEM_AO_BASE,
-};
+static void fmem_master_init(uintptr_t base)
+{
+	/* Domain Remap: TINYSYS to EMI (3-bit to 4-bit)
+	 *    1. SCP from 3 to 3
+	 *    2. others from XXX to 15
+	 */
+	SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0),
+			FOUR_BIT_DOM_REMAP_0, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_1, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_2, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_3, MAS_DOMAIN_3,
+			FOUR_BIT_DOM_REMAP_4, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_5, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_6, MAS_DOMAIN_15,
+			FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15);
+}
 
-static void (*master_init[DEVAPC_AO_MAX])(uintptr_t) = {
-	infra_master_init,
-	peri_master_init,
+struct devapc_init {
+	uintptr_t base;
+	void (*init)(uintptr_t base);
+} devapc_init[DEVAPC_AO_MAX] = {
+	{ DEVAPC_INFRA_AO_BASE, infra_master_init },
+	{ DEVAPC_PERI_AO_BASE, peri_master_init },
+	{ DEVAPC_PERI2_AO_BASE, NULL },
+	{ DEVAPC_PERI_PAR_AO_BASE, NULL },
+	{ DEVAPC_FMEM_AO_BASE, fmem_master_init },
 };
 
 void dapc_init(void)
 {
 	int i;
 	uintptr_t devapc_ao_base;
+	void (*init_func)(uintptr_t base);
 
-	for (i = 0; i < ARRAY_SIZE(devapc_base); i++) {
-		devapc_ao_base = devapc_base[i];
+	for (i = 0; i < ARRAY_SIZE(devapc_init); i++) {
+		devapc_ao_base = devapc_init[i].base;
+		init_func = devapc_init[i].init;
 
 		/* Init dapc */
 		write32(getreg(devapc_ao_base, AO_APC_CON), 0x0);
 		write32(getreg(devapc_ao_base, AO_APC_CON), 0x1);
 
 		/* Init master */
-		if (master_init[i])
-			master_init[i](devapc_ao_base);
+		if (init_func)
+			init_func(devapc_ao_base);
 	}
 }