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authorCK Hu <ck.hu@mediatek.com>2020-06-16 11:54:38 +0800
committerHung-Te Lin <hungte@chromium.org>2020-10-23 03:58:45 +0000
commit3398f3152cf005d1e8219feacac1e1ec4fe50095 (patch)
treea48952d88a85c011e4f401d4fd821c2e6d268a9e /src/soc/mediatek/mt8192/Makefile.inc
parent9190345bf071261a0764c9cfbe1472f974e2bd19 (diff)
soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/Makefile.inc')
-rw-r--r--src/soc/mediatek/mt8192/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index fb3b11de8c..8b2831cc6b 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -30,6 +30,7 @@ ramstage-y += flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
ramstage-y += emi.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/mmu_operations.c mmu_operations.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-y += soc.c
ramstage-y += ../common/timer.c