soc/mediatek/mt8188: Add I2C driver support

Add I2C controller drivers.

TEST=build pass
BUG=b:233720142

Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com>
Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 200 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc
index ddc0011adc..100dde2377 100644
--- a/src/soc/mediatek/mt8188/Makefile.inc
+++ b/src/soc/mediatek/mt8188/Makefile.inc
@@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8188),y)
 
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
+all-y += ../common/i2c.c i2c.c
 all-$(CONFIG_SPI_FLASH) += spi.c
 all-y += ../common/timer.c ../common/timer_prepare.c
 all-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8188/i2c.c b/src/soc/mediatek/mt8188/i2c.c
new file mode 100644
index 0000000000..2c1fcf0a16
--- /dev/null
+++ b/src/soc/mediatek/mt8188/i2c.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8188 Functional Specification
+ * Chapter number: 5.11
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/i2c_simple.h>
+#include <device/mmio.h>
+#include <soc/i2c.h>
+#include <soc/gpio.h>
+
+struct mtk_i2c mtk_i2c_bus_controller[] = {
+	[0] = {
+		.i2c_regs = (void *)(I2C0_BASE),
+		.i2c_dma_regs = (void *)(I2C0_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[1] = {
+		.i2c_regs = (void *)(I2C1_BASE),
+		.i2c_dma_regs = (void *)(I2C1_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[2] = {
+		.i2c_regs = (void *)(I2C2_BASE),
+		.i2c_dma_regs = (void *)(I2C2_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[3] = {
+		.i2c_regs = (void *)(I2C3_BASE),
+		.i2c_dma_regs = (void *)(I2C3_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[4] = {
+		.i2c_regs = (void *)(I2C4_BASE),
+		.i2c_dma_regs = (void *)(I2C4_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[5] = {
+		.i2c_regs = (void *)(I2C5_BASE),
+		.i2c_dma_regs = (void *)(I2C5_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+	[6] = {
+		.i2c_regs = (void *)(I2C6_BASE),
+		.i2c_dma_regs = (void *)(I2C6_DMA_BASE),
+		.mt_i2c_flag = I2C_APDMA_ASYNC,
+	},
+};
+
+_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER,
+	       "Wrong size of mtk_i2c_bus_controller");
+
+struct pad_func {
+	gpio_t gpio;
+	u8 func;
+};
+
+#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
+
+static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = {
+	[0] = {
+		PAD_FUNC(SDA0, SDA0),
+		PAD_FUNC(SCL0, SCL0),
+	},
+	[1] = {
+		PAD_FUNC(SDA1, SDA1),
+		PAD_FUNC(SCL1, SCL1),
+	},
+	[2] = {
+		PAD_FUNC(SDA2, SDA2),
+		PAD_FUNC(SCL2, SCL2),
+	},
+	[3] = {
+		PAD_FUNC(SDA3, SDA3),
+		PAD_FUNC(SCL3, SCL3),
+	},
+	[4] = {
+		PAD_FUNC(SDA4, SDA4),
+		PAD_FUNC(SCL4, SCL4),
+	},
+	[5] = {
+		PAD_FUNC(SDA5, SDA5),
+		PAD_FUNC(SCL5, SCL5),
+	},
+	[6] = {
+		PAD_FUNC(SDA6, SDA6),
+		PAD_FUNC(SCL6, SCL6),
+	},
+};
+
+static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
+{
+	assert(bus < I2C_BUS_NUMBER);
+
+	const struct pad_func *ptr = i2c_funcs[bus];
+	for (size_t i = 0; i < 2; i++) {
+		gpio_set_mode(ptr[i].gpio, ptr[i].func);
+		gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP);
+	}
+}
+
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
+{
+	mtk_i2c_speed_init(bus, speed);
+	mtk_i2c_set_gpio_pinmux(bus);
+}
+
+void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs)
+{
+	printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n",
+	       read32(&regs->ltiming),
+	       read32(&regs->clock_div));
+}
+
+void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl)
+{
+	write32(&regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
+	write32(&regs->timing, bus_ctrl->ac_timing.htiming);
+	write32(&regs->ltiming, bus_ctrl->ac_timing.ltiming);
+	write32(&regs->hs, bus_ctrl->ac_timing.hs);
+	write32(&regs->ext_conf, bus_ctrl->ac_timing.ext);
+}
diff --git a/src/soc/mediatek/mt8188/include/soc/i2c.h b/src/soc/mediatek/mt8188/include/soc/i2c.h
new file mode 100644
index 0000000000..1e46f29ef7
--- /dev/null
+++ b/src/soc/mediatek/mt8188/include/soc/i2c.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8188 Functional Specification
+ * Chapter number: 5.11
+ */
+
+#ifndef SOC_MEDIATEK_MT8188_I2C_H
+#define SOC_MEDIATEK_MT8188_I2C_H
+
+#include <soc/i2c_common.h>
+#include <soc/pll.h>
+
+/* I2C Register */
+struct mt_i2c_regs {
+	uint32_t data_port;
+	uint32_t reserved0[1];
+	uint32_t intr_mask;
+	uint32_t intr_stat;
+	uint32_t control;
+	uint32_t transfer_len;
+	uint32_t transac_len;
+	uint32_t delay_len;
+	uint32_t timing;
+	uint32_t start;
+	uint32_t ext_conf;
+	uint32_t ltiming;
+	uint32_t hs;
+	uint32_t io_config;
+	uint32_t fifo_addr_clr;
+	uint32_t reserved1[2];
+	uint32_t transfer_aux_len;
+	uint32_t clock_div;
+	uint32_t time_out;
+	uint32_t softreset;
+	uint32_t reserved2[16];
+	uint32_t slave_addr;
+	uint32_t reserved3[19];
+	uint32_t debug_stat;
+	uint32_t debug_ctrl;
+	uint32_t reserved4[2];
+	uint32_t fifo_stat;
+	uint32_t fifo_thresh;
+	uint32_t reserved5[897];
+	uint32_t sec_control;
+	uint32_t reserved6[31];
+	uint32_t channel_lock;
+	uint32_t channel_sec;
+	uint32_t hw_cg_en;
+	uint32_t reserved7[1];
+	uint32_t dma_req;
+	uint32_t dma_nreq;
+};
+
+/* I2C ID Number*/
+enum {
+	I2C0,
+	I2C1,
+	I2C2,
+	I2C3,
+	I2C4,
+	I2C5,
+	I2C6,
+};
+
+#define I2C_BUS_NUMBER	7
+#define MAX_CLOCK_DIV	32
+#define I2C_CLK_HZ (124800000)
+
+check_member(mt_i2c_regs, dma_nreq, 0xf94);
+
+void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
+
+#endif /* SOC_MEDIATEK_MT8188_I2C_H */