diff options
| author | Xi Chen <xixi.chen@mediatek.corp-partner.google.com> | 2022-07-26 10:57:32 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-27 15:55:54 +0000 |
| commit | 0c4a39651d2ebbf61402458a21ba5881f694a2b8 (patch) | |
| tree | 73593e44513abf939734ad29074f5aefb187780b /src/soc/mediatek/mt8188/include | |
| parent | bcaa87d603441b74b7f1cf504bf7cb03aa8dafc9 (diff) | |
soc/mediatek/mt8188: Add DRAM fast calibration support
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to
run fast calibration for MT8188 using blob.
DRAM fast calibration logs:
DRAM-K: Fast calibration passed in 19530 msecs
dram size (romstage): 0x200000000
TEST=Fast calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8188/include')
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/dramc_param.h | 65 |
1 files changed, 64 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8188/include/soc/dramc_param.h b/src/soc/mediatek/mt8188/include/soc/dramc_param.h index 225872b7c3..88e2a90e61 100644 --- a/src/soc/mediatek/mt8188/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8188/include/soc/dramc_param.h @@ -21,7 +21,70 @@ #define DRAMC_PARAM_HEADER_VERSION 1 struct sdram_params { - /* Not needed for full calibration */ + /* rank, cbt */ + u32 rank_num; + u32 dram_cbt_mode; + + u16 delay_cell_timex100; + u8 u18ph_dly; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP4 + 1]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* cbt */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_range[CHANNEL_MAX][RANK_MAX]; + s16 cbt_cmd_dly[CHANNEL_MAX]; + u16 cbt_cs_dly[CHANNEL_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* gating */ + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + + /* rx input buffer */ + s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP4]; + s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP4]; + + /* tx perbit */ + u8 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX]; + u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* rx perbit */ + u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4]; + s16 rx_perbit_begin; + + /* dcm */ + u8 best_u[CHANNEL_MAX][RANK_MAX]; + u8 best_l[CHANNEL_MAX][RANK_MAX]; + + /* tx oe */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; + u8 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; + + /* imp k */ + u8 sw_impedance[IMP_DRV_MAX]; }; struct dramc_data { |