diff options
author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-06-01 18:38:56 +0800 |
---|---|---|
committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-03 15:27:26 +0000 |
commit | f0604afa02a62837734b6cc212d6ff1d6c98ba66 (patch) | |
tree | 0b1ca5922ef4969f90b26d34fc1dfb735ba9fe71 /src/soc/mediatek/mt8186 | |
parent | cdc1de7e9237cc3628d2262ee852b5b4b56c56ef (diff) |
soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req()
To simplify the calling sequence for mtk_wdt_preinit() and we always
adjust request setting in mtk_wdt_preinit(), we rename
mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init().
From this modification, we can also enable thermal hardware reset
feature (CB:64676, CB:64675) in MT8192 and MT8195.
BUG=none
TEST=build pass
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186')
-rw-r--r-- | src/soc/mediatek/mt8186/bootblock.c | 1 | ||||
-rw-r--r-- | src/soc/mediatek/mt8186/wdt.c | 2 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8186/bootblock.c b/src/soc/mediatek/mt8186/bootblock.c index 29de7fbe77..e5d1e73047 100644 --- a/src/soc/mediatek/mt8186/bootblock.c +++ b/src/soc/mediatek/mt8186/bootblock.c @@ -12,7 +12,6 @@ void bootblock_soc_init(void) { mtk_mmu_init(); bustracker_init(); - mtk_wdt_preinit(); mtk_wdt_init(); mt_pll_init(); unmask_eint_event_mask(); diff --git a/src/soc/mediatek/mt8186/wdt.c b/src/soc/mediatek/mt8186/wdt.c index 39bc2835c8..5303f9d566 100644 --- a/src/soc/mediatek/mt8186/wdt.c +++ b/src/soc/mediatek/mt8186/wdt.c @@ -20,7 +20,7 @@ DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0) DEFINE_BIT(MTK_WDT_THERMAL_EN, 18) DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 18) -void mtk_wdt_preinit(void) +void mtk_wdt_set_req(void) { SET32_BITFIELDS(&mtk_wdt->wdt_req_mode, MTK_WDT_SPM_THERMAL_EN, 0, |