soc/mediatek/mt8186: Support DRAM fast calibration using blob

For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external
program (e.g., the "DRAM blob") to do the full DRAM calibration first,
then store and and apply the generated parameters to the reference
"fast DRAM calibration" in the vendor/mediatek folder for normal system
boot.

Starting with MT8186 the implementation of fast calibration may need
to be changed, and a "DRAM blob" only path is introduced for devices
that have to do both full and fast calibration using the external blob.

TEST=fast calibration pass on kingler/krabby
BUG=b:204226005

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 35 insertions, 13 deletions

diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig
index 11a18f2e10..654baf20d0 100644
--- a/src/soc/mediatek/mt8186/Kconfig
+++ b/src/soc/mediatek/mt8186/Kconfig
@@ -9,6 +9,7 @@ config SOC_MEDIATEK_MT8186
 	select CACHE_MRC_SETTINGS
 	select HAVE_UART_SPECIAL
 	select SOC_MEDIATEK_COMMON
+	select MEDIATEK_BLOB_FAST_INIT
 
 if SOC_MEDIATEK_MT8186
 
diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_param.h b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
index 5559b0a914..b5c019fbff 100644
--- a/src/soc/mediatek/mt8186/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8186/include/soc/dramc_param.h
@@ -59,48 +59,53 @@ struct sdram_info {
 };
 
 struct sdram_params {
+	/* Sometimes, we may need to compare params member
+	 * between coreboot and blob for analysis. Here,
+	 * add member size using xxxB.
+	 */
+	/* 4 + 4 = 8B */
 	u32 rank_num;
 	u16 num_dlycell_perT;
 	u16 delay_cell_timex100;
 
-	/* duty */
+	/* duty 16B */
 	s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
 	s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
-	s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
 	s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
 	s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
 
-	/* CBT */
+	/* CBT 48B */
 	u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
-	s8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX];
+	u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX];
 	u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX];
 	u8 cbt_ca_prebit_dly[CHANNEL_MAX][RANK_MAX][DQS_BIT_NUMBER];
 
-	/* write leveling */
+	/* write leveling 8B */
 	u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 
-	/* Gating */
+	/* Gating 32B */
 	u8 gating_MCK[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 
-	/* TX perbit */
+	/* TX perbit 164B */
 	u8 tx_window_vref[CHANNEL_MAX][RANK_MAX];
 	u16 tx_center_min[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u16 tx_center_max[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u16 tx_win_center[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
 
-	/* rx datlat */
+	/* rx datlat 4B */
 	u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
 
-	/* RX perbit */
+	/* RX perbit 88B */
 	u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
-	u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
+	u8 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
+	u8 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
 
-	/* TX OE */
+	/* TX OE 16B */
 	u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 	u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
 };
@@ -112,6 +117,15 @@ struct emi_mdl {
 	u32 chn_cona_val;
 };
 
+struct ddr_mrr_info {
+	u16 mr5_vendor_id;
+	u16 mr6_revision_id;
+	u16 mr7_revision_id;
+	u64 mr8_density[RANK_MAX];
+	u32 rank_nums;
+	u8 die_num[RANK_MAX];
+};
+
 struct ddr_base_info {
 	u32 config_dvfs;		/* SDRAM_DVFS_FLAG */
 	struct sdram_info sdram;
@@ -120,6 +134,8 @@ struct ddr_base_info {
 	u64 rank_size[RANK_MAX];
 	struct emi_mdl emi_config;
 	DRAM_CBT_MODE_T cbt_mode[RANK_MAX];
+	struct ddr_mrr_info mrr_info;
+	u32 data_rate;
 };
 
 struct dramc_data {
diff --git a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
index 34e8414d47..5602e144cb 100644
--- a/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
+++ b/src/soc/mediatek/mt8186/include/soc/dramc_soc.h
@@ -15,6 +15,11 @@ typedef enum {
 	RANK_MAX,
 } DRAM_RANK_T;
 
+typedef enum {
+	RANK_SINGLE = 1,
+	RANK_DUAL,
+} DRAM_RANK_NUMBER_T;
+
 /* DRAM SHUFFLE RG type */
 typedef enum {
 	DRAM_DFS_SHUFFLE_1 = 0,