diff options
author | Bo-Chen Chen <rex-bc.chen@mediatek.com> | 2022-08-29 19:09:38 +0800 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-31 16:47:52 +0000 |
commit | 9d638a95167781671dd0f982b1e6c2194c7f22eb (patch) | |
tree | a43e20a14c4a4caef0691818a7121532b6143f75 /src/soc/mediatek/mt8186/spm.c | |
parent | dcdbda5c93bedbce202e2f55903a7f52dd4f84f6 (diff) |
soc/mediatek: Move some SPM functions to common
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and
MT8188, so we move them to common/spm.c.
TEST=build pass.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186/spm.c')
-rw-r--r-- | src/soc/mediatek/mt8186/spm.c | 172 |
1 files changed, 8 insertions, 164 deletions
diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index cc4164f47f..00e2c27d86 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -6,15 +6,8 @@ */ #include <assert.h> -#include <console/console.h> -#include <delay.h> #include <soc/mcu_common.h> #include <soc/spm.h> -#include <soc/spm_common.h> -#include <soc/symbols.h> -#include <timer.h> - -#define SPM_SYSTEM_BASE_OFFSET 0x40000000 static const struct pwr_ctrl spm_init_ctrl = { /* For SPM, this flag is not auto-gen. */ @@ -187,7 +180,7 @@ static const struct pwr_ctrl spm_init_ctrl = { /* Auto-gen End */ }; -static void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) { /* Auto-gen Start */ @@ -383,7 +376,7 @@ static void spm_hw_s1_state_monitor(int en) SPM_ACK_CHK_3_CON_EN_1, 0); } -static void spm_register_init(void) +void spm_register_init(void) { /* Enable register control */ write32(&mtk_spm->poweron_config_set, @@ -450,36 +443,19 @@ static void spm_register_init(void) spm_hw_s1_state_monitor(0); } -static void spm_extern_initialize(void) +void spm_extern_initialize(void) { SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1, INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1); } -static void spm_set_sysclk_settle(void) -{ - write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); -} - -static void spm_code_swapping(void) -{ - u32 mask; - - mask = read32(&mtk_spm->spm_wakeup_event_mask); - write32(&mtk_spm->spm_wakeup_event_mask, - mask & ~SPM_WAKEUP_EVENT_MASK_BIT0); - write32(&mtk_spm->spm_cpu_wakeup_event, 1); - write32(&mtk_spm->spm_cpu_wakeup_event, 0); - write32(&mtk_spm->spm_wakeup_event_mask, mask); -} - -static void spm_reset_and_init_pcm(void) +void spm_reset_and_init_pcm(void) { bool first_load_fw = true; /* Check whether the SPM FW is running */ - if (read32((void *)MD32PCM_CFGREG_SW_RSTN) & MD32PCM_CFGREG_SW_RSTN_RUN) + if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & MD32PCM_CFGREG_SW_RSTN_RUN) first_load_fw = false; if (!first_load_fw) { @@ -506,55 +482,7 @@ static void spm_reset_and_init_pcm(void) SPM_REGWR_CFG_KEY | RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); } -static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) -{ - uintptr_t ptr; - u32 dmem_words; - u32 pmem_words; - u32 total_words; - u32 pmem_start; - u32 dmem_start; - - ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; - pmem_words = pcm->desc.pmem_words; - total_words = pcm->desc.total_words; - dmem_words = total_words - pmem_words; - pmem_start = pcm->desc.pmem_start; - dmem_start = pcm->desc.dmem_start; - - printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", - __func__, (long)ptr, pmem_words, dmem_words); - - /* DMA needs 16-byte aligned source data. */ - assert(ptr % 16 == 0); - - write32((void *)MD32PCM_DMA0_SRC, ptr); - write32((void *)MD32PCM_DMA0_DST, pmem_start); - write32((void *)MD32PCM_DMA0_WPPT, pmem_words); - write32((void *)MD32PCM_DMA0_WPTO, dmem_start); - write32((void *)MD32PCM_DMA0_COUNT, total_words); - write32((void *)MD32PCM_DMA0_CON, MD32PCM_DMA0_CON_VAL); - write32((void *)MD32PCM_DMA0_START, MD32PCM_DMA0_START_VAL); - - setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); -} - -static void spm_init_pcm_register(void) -{ - /* Init r0 with POWER_ON_VAL0 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val0)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); - write32(&mtk_spm->pcm_pwr_io_en, 0); - - /* Init r7 with POWER_ON_VAL1 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val1)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); - write32(&mtk_spm->pcm_pwr_io_en, 0); -} - -static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) { u32 val, mask; @@ -596,91 +524,7 @@ static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) SYS_TIMER_START_EN_LSB, 0); } -static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +const struct pwr_ctrl *get_pwr_ctrl(void) { - u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; - - /* Set PCM flags and data */ - if (pwrctrl->pcm_flags_cust_clr != 0) - pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; - if (pwrctrl->pcm_flags_cust_set != 0) - pcm_flags |= pwrctrl->pcm_flags_cust_set; - if (pwrctrl->pcm_flags1_cust_clr != 0) - pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; - if (pwrctrl->pcm_flags1_cust_set != 0) - pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; - - write32(&mtk_spm->spm_sw_flag_0, pcm_flags); - write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); - write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); - write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); -} - -static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) -{ - /* Waiting for loading SPMFW done*/ - while (read32((void *)MD32PCM_DMA0_RLCT) != 0x0) - ; - - /* Init register to match PCM expectation */ - write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); - write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF); - write32(&mtk_spm->pcm_reg_data_ini, 0); - - spm_set_pcm_flags(pwrctrl); - - /* Kick PCM to run (only toggle PCM_KICK) */ - setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); - - /* Reset md32pcm */ - SET32_BITFIELDS((void *)MD32PCM_CFGREG_SW_RSTN, - MD32PCM_CFGREG_SW_RSTN_RESET, 1); - - /* Waiting for SPM init done */ - udelay(SPM_INIT_DONE_US); -} - -static void reset_spm(struct mtk_mcu *mcu) -{ - struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv; - - spm_parse_firmware(mcu); - spm_reset_and_init_pcm(); - spm_kick_im_to_fetch(pcm); - spm_init_pcm_register(); - spm_set_wakeup_event(&spm_init_ctrl); - spm_kick_pcm_to_run(&spm_init_ctrl); -} - -static struct mtk_mcu spm = { - .firmware_name = CONFIG_SPM_FIRMWARE, - .reset = reset_spm, -}; - -int spm_init(void) -{ - struct dyna_load_pcm pcm; - struct stopwatch sw; - - stopwatch_init(&sw); - - spm_register_init(); - spm_set_power_control(&spm_init_ctrl); - spm_set_sysclk_settle(); - spm_extern_initialize(); - - spm.load_buffer = _dram_dma; - spm.buffer_size = REGION_SIZE(dram_dma); - spm.priv = (void *)&pcm; - - if (mtk_init_mcu(&spm)) { - printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__); - return -1; - } - - printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n", - __func__, stopwatch_duration_msecs(&sw), - read32(&mtk_spm->md32pcm_pc)); - - return 0; + return &spm_init_ctrl; } |