diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2022-02-11 16:10:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-02 13:13:24 +0000 |
| commit | c89f252608d87d7db7731fdd9c80b4bed0e33b9b (patch) | |
| tree | 55e8ed54eefdb222097f73bed1e208a19b760e16 /src/soc/mediatek/mt8186/include | |
| parent | 025fb1737203b4a9ff1eb3b57ff9c28fc89cb16d (diff) | |
soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.
This implementation is according to chapter 5.13 in MT8186 Functional
Specification.
BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8186/include')
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/rtc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h index 3a0c7cd100..a3fb7a099f 100644 --- a/src/soc/mediatek/mt8186/include/soc/rtc.h +++ b/src/soc/mediatek/mt8186/include/soc/rtc.h @@ -143,6 +143,7 @@ enum { PMIC_RG_DCXO_CW00 = 0x0788, PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW03 = 0x0794, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, PMIC_RG_DCXO_CW11 = 0x07A2, |