diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2022-01-24 13:09:14 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2022-01-26 02:56:05 +0000 |
| commit | 978930e860fdd1f5efa013ae12bc564fef7e8bef (patch) | |
| tree | cd8c5b5f4e159a354973dfe9b9d7eff133d5e3aa /src/soc/mediatek/mt8186/include | |
| parent | a36f9ab04176e2dd4b896d2aa2ef1e552982e571 (diff) | |
soc/mediatek/mt8186: Update PWRAP arbiter enable bit
There is no wakeup source when we test function of suspend and resume.
The root cause is that the monitor enable bit of PWRAP is not configured
correctly.
BUG=b:213255218, b:214978483
TEST=receive wakeup source from MT6366 successfully
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8186/include')
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/pmic_wrap.h | 35 |
1 files changed, 22 insertions, 13 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h index 4091485155..78f7034b61 100644 --- a/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h +++ b/src/soc/mediatek/mt8186/include/soc/pmic_wrap.h @@ -362,22 +362,31 @@ enum { }; enum { - ARB_WACS0 = 0x1, + ARB_WACS0 = 0x1 << 0, + ARB_WACS1 = 0x1 << 1, ARB_WACS2 = 0x1 << 2, + ARB_WACS3 = 0x1 << 3, ARB_WACS_P2P = 0x1 << 4, ARB_WACS_MD32 = 0x1 << 5, - ARB_MD = 0x1 << 6, - ARB_WACS_POWER_HW = 0x1 << 9, - ARB_DCXO_CONN = 0x1 << 11, - ARB_DCXO_NFC = 0x1 << 12, - ARB_MD_ADC0 = 0x1 << 13, - ARB_MD_ADC1 = 0x1 << 14, - ARB_GPS_0 = 0x1 << 15, - ARB_GPS_1 = 0x1 << 16, - STAUPD_HARB = 0x1 << 17, - ARB_USER_EN = ARB_WACS0 | ARB_WACS2 | ARB_WACS_P2P | ARB_WACS_MD32 | - ARB_MD | ARB_WACS_POWER_HW | ARB_DCXO_CONN | ARB_DCXO_NFC | - ARB_MD_ADC0 | ARB_MD_ADC1 | ARB_GPS_0 | ARB_GPS_1 | STAUPD_HARB, + ARB_MDINF = 0x1 << 6, + ARB_C2KINF = 0x1 << 7, + ARB_MD_DVFSINF = 0x1 << 8, + ARB_SPMINF = 0x1 << 9, + ARB_SPMINF_BACKUP = 0x1 << 10, + ARB_SRCLKEN_RCINF = 0x1 << 11, + ARB_DCXO_CONNINF = 0x1 << 12, + ARB_DCXO_NFCINF = 0x1 << 13, + ARB_MCU_PMINF = 0x1 << 14, + ARB_MD_ADCINF_0 = 0x1 << 15, + ARB_MD_ADCINF_1 = 0x1 << 16, + ARB_GPSINF_0 = 0x1 << 17, + ARB_GPSINF_1 = 0x1 << 18, + ARB_STAUPD = 0x1 << 19, + ARB_USER_EN = ARB_WACS0 | ARB_WACS1 | ARB_WACS2 | ARB_WACS3 | + ARB_WACS_P2P | ARB_WACS_MD32 | ARB_MDINF | + ARB_MD_DVFSINF | ARB_SPMINF | + ARB_DCXO_CONNINF | ARB_DCXO_NFCINF | ARB_MD_ADCINF_0 | + ARB_MD_ADCINF_1 | ARB_GPSINF_0 | ARB_GPSINF_1 | ARB_STAUPD, }; enum { |