soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoC

Add new folder and basic drivers for Mediatek SoC 'MT8186'.

Difference of modules including in this patch between MT8186 and existing SoCs:
Timer:
	Similar to MT8195, MT8186 uses v2 timer.
EMI/PLL/SPI:
	Different from existing SoCs.

TEST=boot from SPI-NOR and show uart log on MT8186 EVB
BUG=b:200134633

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 196 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h
new file mode 100644
index 0000000000..20a48addfd
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
+#define __SOC_MEDIATEK_MT8186_INCLUDE_SOC_ADDRESSMAP_H__
+
+enum {
+	MCUSYS_BASE	= 0x0C530000,
+	IO_PHYS		= 0x10000000,
+};
+
+enum {
+	MCUCFG_BASE		= MCUSYS_BASE + 0x00008000,
+};
+
+enum {
+	CKSYS_BASE			= IO_PHYS + 0x00000000,
+	INFRACFG_AO_BASE		= IO_PHYS + 0x00001000,
+	IOCFG_LT_BASE			= IO_PHYS + 0x00002000,
+	IOCFG_LM_BASE			= IO_PHYS + 0x00002200,
+	IOCFG_LB_BASE			= IO_PHYS + 0x00002400,
+	IOCFG_BL_BASE			= IO_PHYS + 0x00002600,
+	IOCFG_RB_BASE			= IO_PHYS + 0x00002A00,
+	IOCFG_RT_BASE			= IO_PHYS + 0x00002C00,
+	GPIO_BASE			= IO_PHYS + 0x00005000,
+	SPM_BASE			= IO_PHYS + 0x00006000,
+	RGU_BASE			= IO_PHYS + 0x00007000,
+	GPT_BASE			= IO_PHYS + 0x00008000,
+	EINT_BASE			= IO_PHYS + 0x0000B000,
+	APMIXED_BASE			= IO_PHYS + 0x0000C000,
+	DEVAPC_AO_INFRA_PERI_BASE	= IO_PHYS + 0x0000E000,
+	DEVAPC_AO_MM_BASE		= IO_PHYS + 0x0000F000,
+	SYSTIMER_BASE			= IO_PHYS + 0x00017000,
+	I2C0_DMA_BASE			= IO_PHYS + 0x00200100,
+	I2C1_DMA_BASE			= IO_PHYS + 0x00200200,
+	I2C2_DMA_BASE			= IO_PHYS + 0x00200300,
+	I2C3_DMA_BASE			= IO_PHYS + 0x00200480,
+	I2C4_DMA_BASE			= IO_PHYS + 0x00200580,
+	I2C5_DMA_BASE			= IO_PHYS + 0x00200700,
+	I2C6_DMA_BASE			= IO_PHYS + 0x00200800,
+	I2C7_DMA_BASE			= IO_PHYS + 0x00200900,
+	I2C8_DMA_BASE			= IO_PHYS + 0x00200A80,
+	I2C9_DMA_BASE			= IO_PHYS + 0x00200C00,
+	DEVAPC_BASE			= IO_PHYS + 0x00207000,
+	EMI0_BASE			= IO_PHYS + 0x00219000,
+	EMI0_MPU_BASE			= IO_PHYS + 0x0021B000,
+	DRAMC_CHA_AO_BASE		= IO_PHYS + 0x00220000,
+	SFLASH_REG_BASE			= IO_PHYS + 0x01000000,
+	AUXADC_BASE			= IO_PHYS + 0x01001000,
+	UART0_BASE			= IO_PHYS + 0x01002000,
+	I2C7_BASE			= IO_PHYS + 0x01004000,
+	I2C8_BASE			= IO_PHYS + 0x01005000,
+	I2C0_BASE			= IO_PHYS + 0x01007000,
+	I2C1_BASE			= IO_PHYS + 0x01008000,
+	I2C2_BASE			= IO_PHYS + 0x01009000,
+	SPI0_BASE			= IO_PHYS + 0x0100A000,
+	I2C6_BASE			= IO_PHYS + 0x0100D000,
+	I2C3_BASE			= IO_PHYS + 0x0100F000,
+	SPI1_BASE			= IO_PHYS + 0x01010000,
+	I2C4_BASE			= IO_PHYS + 0x01011000,
+	SPI2_BASE			= IO_PHYS + 0x01012000,
+	SPI3_BASE			= IO_PHYS + 0x01013000,
+	SPI4_BASE			= IO_PHYS + 0x01014000,
+	SPI5_BASE			= IO_PHYS + 0x01015000,
+	I2C5_BASE			= IO_PHYS + 0x01016000,
+	I2C9_BASE			= IO_PHYS + 0x01019000,
+	SSUSB_IPPC_BASE			= IO_PHYS + 0x01203E00,
+	MSDC0_BASE			= IO_PHYS + 0x01230000,
+	SSUSB_SIF_BASE			= IO_PHYS + 0x01CA0000,
+	EFUSEC_BASE			= IO_PHYS + 0x01CB0000,
+	MIPITX_BASE			= IO_PHYS + 0x01CC0000,
+	MSDC0_TOP_BASE			= IO_PHYS + 0x01CD0000,
+	SMI_BASE			= IO_PHYS + 0x04002000,
+	SMI_LARB0			= IO_PHYS + 0x04003000,
+	DSI0_BASE			= IO_PHYS + 0x04013000,
+};
+#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/emi.h b/src/soc/mediatek/mt8186/include/soc/emi.h
new file mode 100644
index 0000000000..decfa07a2e
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/emi.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 4.8
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_EMI_H
+#define SOC_MEDIATEK_MT8186_EMI_H
+
+#include <stddef.h>
+
+size_t sdram_size(void);
+
+#endif /* SOC_MEDIATEK_MT8186_EMI_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/memlayout.ld b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
new file mode 100644
index 0000000000..a1700e60b5
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/memlayout.ld
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/*
+ * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
+ * It will be returned before starting the ramstage.
+ * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
+ */
+#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
+#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
+#define DRAM_INIT_CODE(addr, size) \
+	REGION(dram_init_code, addr, size, 64K)
+
+#define DRAM_DMA(addr, size) \
+	REGION(dram_dma, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
+SECTIONS
+{
+	SRAM_START(0x00100000)
+	VBOOT2_WORK(0x00100000, 12K)
+	STACK(0x00103000, 8K)
+	TTB(0x00105000, 28K)
+	DMA_COHERENT(0x0010C000, 4K)
+	TPM_TCPA_LOG(0x0010D000, 2K)
+	FMAP_CACHE(0x0010D800, 2K)
+	WATCHDOG_TOMBSTONE(0x0010E000, 4)
+	CBFS_MCACHE(0x0010E004, 7K - 4)
+	TIMESTAMP(0x0010FC00, 1K)
+	/* MT8186 has 64KB SRAM. */
+	SRAM_END(0x00110000)
+
+	SRAM_L2C_START(0x00200000)
+	/* 4K reserved for BOOTROM until BOOTBLOCK is started */
+	BOOTBLOCK(0x00201000, 60K)
+	/*
+	 * The needed size can be obtained by:
+	 *  aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz
+	 */
+	DRAM_INIT_CODE(0x00210000, 240K)
+	OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K)
+	PRERAM_CBFS_CACHE(0x00290000, 48K)
+	PRERAM_CBMEM_CONSOLE(0x0029C000, 400K)
+	SRAM_L2C_END(0x00300000)
+
+	DRAM_START(0x40000000)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 2M)
+	RAMSTAGE(0x40300000, 256K)
+
+	BL31(0x54600000, 0x60000)
+}
diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
new file mode 100644
index 0000000000..0634a3b72e
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 3.2
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_PLL_H
+#define SOC_MEDIATEK_MT8186_PLL_H
+
+#include <soc/pll_common.h>
+
+/* top_div rate */
+enum {
+	CLK26M_HZ	= 26 * MHz,
+};
+
+/* top_mux rate */
+enum {
+	UART_HZ		= CLK26M_HZ,
+};
+
+#endif /* SOC_MEDIATEK_MT8186_PLL_H */
diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h
new file mode 100644
index 0000000000..cf64660837
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/spi.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 5.6
+ */
+
+#ifndef MTK_MT8186_SPI_H
+#define MTK_MT8186_SPI_H
+
+#include <spi-generic.h>
+
+#endif
diff --git a/src/soc/mediatek/mt8186/include/soc/timer.h b/src/soc/mediatek/mt8186/include/soc/timer.h
new file mode 100644
index 0000000000..24d85295ce
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/timer.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 5.13
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_TIMER_H
+#define SOC_MEDIATEK_MT8186_TIMER_H
+
+#include <soc/timer_v2.h>
+
+#endif