diff options
| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2022-10-04 13:37:56 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 16:03:06 +0000 |
| commit | 2caa2fc56e703fd01e94ebdb0f8cea5a96a0ae32 (patch) | |
| tree | e6fbea7b79715ca04d12ba2cb050477848de728d /src/soc/mediatek/mt8186/include | |
| parent | a9e595770f4ab4f8142fd88f157758dbaf085daa (diff) | |
soc/mediatek/mt8186: Add DEVAPC settings for ADSP
Add DEVAPC permission settings for ADSP and set its domain number to 6.
TEST=SOF driver is functional.
BUG=b:204229221
Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8186/include')
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8186/include/soc/devapc.h | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index d19a8db17e..33a232740a 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -51,6 +51,7 @@ enum { SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, AUDIODSP_BASE = IO_PHYS + 0x00680000, + DEVAPC_AO_AUD_BASE = IO_PHYS + 0x0069C000, SFLASH_REG_BASE = IO_PHYS + 0x01000000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, diff --git a/src/soc/mediatek/mt8186/include/soc/devapc.h b/src/soc/mediatek/mt8186/include/soc/devapc.h index 26f31cc005..d7bd8bf5da 100644 --- a/src/soc/mediatek/mt8186/include/soc/devapc.h +++ b/src/soc/mediatek/mt8186/include/soc/devapc.h @@ -19,6 +19,8 @@ enum devapc_ao_offset { MAS_DOM_3 = 0x0A0C, MAS_SEC_0 = 0x0B00, AO_APC_CON = 0x0F00, + AUD_DOM_0 = 0x0900, + AUD_SEC_0 = 0x0A00, }; /****************************************************************************** @@ -39,6 +41,7 @@ struct apc_infra_peri_dom_4 { enum devapc_sys_dom_num { DOM_NUM_INFRA_AO_SYS0 = 8, DOM_NUM_MM_AO_SYS0 = 4, + DOM_NUM_AUD_AO_SYS0 = 16, }; enum devapc_cfg_index { @@ -48,6 +51,7 @@ enum devapc_cfg_index { /* PERM_ATTR MACRO */ #define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_8(__VA_ARGS__) } } #define DAPC_MM_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } +#define DAPC_AUD_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_16(__VA_ARGS__) } } /****************************************************************************** * Variable DEFINITION @@ -62,6 +66,7 @@ enum devapc_cfg_index { DEFINE_BIT(SCP_SSPM_SEC, 21) DEFINE_BITFIELD(SPM_DOM, 11, 8) DEFINE_BITFIELD(SCP_DOM, 3, 0) +DEFINE_BITFIELD(ADSP_DOM, 3, 0) /* Domain Remap */ DEFINE_BITFIELD(TWO_BIT_DOM_REMAP_0, 1, 0) |