diff options
| author | Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> | 2021-09-29 17:47:59 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-03 18:57:27 +0000 |
| commit | 09cbb064fcfab857e4d353a1c3dc5e0916d7ee60 (patch) | |
| tree | d7550205127fbfc43608b13dc70d6c943b032fbf /src/soc/mediatek/mt8186/gpio.c | |
| parent | b8fa1d389a013da1314fa95e7e89fd8041279527 (diff) | |
soc/mediatek/mt8186: Add GPIO drivers
Add GPIO drivers to let other module control GPIOs.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8186/gpio.c')
| -rw-r--r-- | src/soc/mediatek/mt8186/gpio.c | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c new file mode 100644 index 0000000000..bd3ab6596c --- /dev/null +++ b/src/soc/mediatek/mt8186/gpio.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.1 + */ + +#include <device/mmio.h> +#include <gpio.h> + +static void *gpio_find_reg_addr(gpio_t gpio) +{ + void *reg_addr; + switch (gpio.base & 0x0f) { + case 1: + reg_addr = (void *)IOCFG_LT_BASE; + break; + case 2: + reg_addr = (void *)IOCFG_LM_BASE; + break; + case 3: + reg_addr = (void *)IOCFG_LB_BASE; + break; + case 4: + reg_addr = (void *)IOCFG_BL_BASE; + break; + case 5: + reg_addr = (void *)IOCFG_RB_BASE; + break; + case 6: + reg_addr = (void *)IOCFG_RT_BASE; + break; + default: + reg_addr = NULL; + break; + } + + return reg_addr; +} + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, BIT(bit)); + else + clrbits32(reg1, BIT(bit)); + } + + if (enable == GPIO_PULL_ENABLE) { + setbits32(reg2, 1 << bit); + } else { + clrbits32(reg2, 1 << bit); + clrbits32(reg2 + 0x010, BIT(bit)); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, BIT(bit)); + setbits32(reg2, BIT(bit)); + } else { + clrbits32(reg2, BIT(bit)); + setbits32(reg1, BIT(bit)); + } + } else { + clrbits32(reg1, BIT(bit)); + clrbits32(reg2, BIT(bit)); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} |