diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2019-04-26 11:58:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:27:24 +0000 |
| commit | 3d96f6040901dea0b83939a9bceb49babe91c614 (patch) | |
| tree | ba65b5e2689e71bcab711fa5503bdc4e4dafc0af /src/soc/mediatek/mt8183 | |
| parent | d95425c51a6cd11a9a22d007afb66ef841359e96 (diff) | |
mediatek: Add function to raise the CPU frequency
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency.
Move the function declaration to common header.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183')
| -rw-r--r-- | src/soc/mediatek/mt8183/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/pll.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 3fce0a81fd..5392a9e635 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -32,6 +32,7 @@ romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c romstage-y += mt8183.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 8608b4ac10..07ce6603f6 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -369,3 +369,8 @@ void mt_pll_init(void) /* enable mtkaif 26m clock */ setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } + +void mt_pll_raise_ca53_freq(u32 freq) +{ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); +} |