soc/mediatek/mt8192: add rtc MT6359P driver

Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor
mt8173 and mt8183 code by extracting common API. Move rtc_read and
rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via
pmic wrapper, while mt8192 accesses it via pmif.

Reference datasheet:
  Document No: RH-D-2018-0101.

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 36 insertions, 105 deletions

diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 744455d5aa..e0ec81012b 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -37,7 +37,7 @@ romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
-romstage-y += ../common/rtc.c rtc.c
+romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/i2c.c i2c.c
 romstage-y += ../common/timer.c
@@ -54,7 +54,7 @@ ramstage-y += ../common/mcu.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += ../common/pmic_wrap.c
-ramstage-y += ../common/rtc.c rtc.c
+ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
 ramstage-y += soc.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += spm.c
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 0e5c598d31..f7c189f5ae 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -3,6 +3,7 @@
 #ifndef SOC_MEDIATEK_MT8183_RTC_H
 #define SOC_MEDIATEK_MT8183_RTC_H
 
+#include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
 
 /* RTC registers */
@@ -203,9 +204,32 @@ enum {
 
 /* external API */
 void rtc_bbpu_power_on(void);
-void rtc_osc_init(void);
-int rtc_init(u8 recover);
+int rtc_init(int recover);
+int rtc_gpio_init(void);
 void rtc_boot(void);
+u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
 
+static inline s32 rtc_read(u16 addr, u16 *rdata)
+{
+	s32 ret;
+
+	ret = pwrap_read(addr, rdata);
+	if (ret < 0)
+		rtc_info("pwrap_read failed: ret=%d\n", ret);
+
+	return ret;
+}
+
+static inline s32 rtc_write(u16 addr, u16 wdata)
+{
+	s32 ret;
+
+	ret = pwrap_write(addr, wdata);
+	if (ret < 0)
+		rtc_info("pwrap_write failed: ret=%d\n", ret);
+
+	return ret;
+}
+
 #endif /* SOC_MEDIATEK_MT8183_RTC_H */
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 400412fffb..41dc5c04af 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -2,8 +2,8 @@
 
 #include <delay.h>
 #include <halt.h>
-#include <soc/rtc_common.h>
 #include <soc/rtc.h>
+#include <soc/rtc_common.h>
 #include <soc/mt6358.h>
 #include <soc/pmic_wrap.h>
 #include <timer.h>
@@ -20,7 +20,7 @@ static int rtc_enable_dcxo(void)
 	rtc_write_trigger();
 
 	mdelay(1);
-	if (!rtc_writeif_unlock()) { /* Unlock for reload */
+	if (!rtc_writeif_unlock()) {
 		rtc_info("rtc_writeif_unlock() failed\n");
 		return 0;
 	}
@@ -44,7 +44,7 @@ static int rtc_enable_dcxo(void)
 }
 
 /* initialize rtc related gpio */
-static int rtc_gpio_init(void)
+int rtc_gpio_init(void)
 {
 	u16 con;
 
@@ -67,7 +67,7 @@ static int rtc_gpio_init(void)
 	return rtc_write_trigger();
 }
 
-static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
+u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 {
 	u16 bbpu, osc32con;
 	u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
@@ -142,93 +142,6 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 	return fqmtr_data;
 }
 
-/* 32k clock calibration */
-static u16 rtc_eosc_cali(void)
-{
-	u16 middle, diff1, diff2, cksel;
-	u16 val = 0;
-	u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END;
-
-	rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
-	cksel &= ~PMIC_FQMTR_CKSEL_MASK;
-	/* select EOSC_32 as fixed clock */
-	rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
-	rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
-	rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel);
-
-	while (left <= right) {
-		middle = (right + left) / 2;
-		if (middle == left)
-			break;
-
-		/* select 26M as target clock */
-		val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
-
-		if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
-			break;
-		if (val > RTC_FQMTR_HIGH_BASE)
-			right = middle;
-		else
-			left = middle;
-	}
-
-	if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
-		return middle;
-
-	val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
-	if (val > RTC_FQMTR_LOW_BASE)
-		diff1 = val - RTC_FQMTR_LOW_BASE;
-	else
-		diff1 = RTC_FQMTR_LOW_BASE - val;
-
-	val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
-	if (val > RTC_FQMTR_LOW_BASE)
-		diff2 = val - RTC_FQMTR_LOW_BASE;
-	else
-		diff2 = RTC_FQMTR_LOW_BASE - val;
-
-	if (diff1 < diff2)
-		return left;
-	else
-		return right;
-}
-
-void rtc_osc_init(void)
-{
-	u16 osc32con;
-
-	/* enable 32K export */
-	rtc_gpio_init();
-
-	/* Calibrate eosc32 for powerdown clock */
-	rtc_read(RTC_OSC32CON, &osc32con);
-	osc32con &= ~RTC_XOSCCALI_MASK;
-	osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
-	rtc_xosc_write(osc32con);
-	rtc_info("EOSC32 cali val = 0x%x\n", osc32con);
-}
-
-/* enable lpd subroutine */
-static int rtc_lpen(u16 con)
-{
-	con &= ~RTC_CON_LPRST;
-	rtc_write(RTC_CON, con);
-	if (!rtc_write_trigger())
-		return 0;
-
-	con |= RTC_CON_LPRST;
-	rtc_write(RTC_CON, con);
-	if (!rtc_write_trigger())
-		return 0;
-
-	con &= ~RTC_CON_LPRST;
-	rtc_write(RTC_CON, con);
-	if (!rtc_write_trigger())
-		return 0;
-
-	return 1;
-}
-
 /* low power detect setting */
 static int rtc_lpd_init(void)
 {
@@ -291,16 +204,8 @@ static bool rtc_hw_init(void)
 	return true;
 }
 
-/* write powerkeys to enable rtc functions */
-static int rtc_powerkey_init(void)
-{
-	rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
-	rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
-	return rtc_write_trigger();
-}
-
 /* rtc init check */
-int rtc_init(u8 recover)
+int rtc_init(int recover)
 {
 	int ret;
 
@@ -320,6 +225,7 @@ int rtc_init(u8 recover)
 
 	rtc_osc_init();
 
+	/* In recovery mode, we need 20ms delay for register setting. */
 	if (recover)
 		mdelay(20);
 
@@ -343,7 +249,8 @@ int rtc_init(u8 recover)
 		goto err;
 	}
 
-	/* After lpd init, powerkeys need to be written again to enable
+	/*
+	 * After lpd init, powerkeys need to be written again to enable
 	 * low power detect function.
 	 */
 	if (!rtc_powerkey_init()) {