Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 24 insertions, 24 deletions

diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 5368077318..ff61303337 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -282,7 +282,7 @@ static const struct rate rates[] = {
 
 void pll_set_pcw_change(const struct pll *pll)
 {
-	setbits_le32(pll->div_reg, PLL_PCW_CHG);
+	setbits32(pll->div_reg, PLL_PCW_CHG);
 }
 
 void mt_pll_init(void)
@@ -290,20 +290,20 @@ void mt_pll_init(void)
 	int i;
 
 	/* enable univpll & mainpll div */
-	setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
+	setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
 
 	/* enable clock square1 low-pass filter */
-	setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
+	setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
 
 	/* xPLL PWR ON */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
+		setbits32(plls[i].pwr_reg, PLL_PWR_ON);
 
 	udelay(PLL_PWR_ON_DELAY);
 
 	/* xPLL ISO Disable */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		clrbits_le32(plls[i].pwr_reg, PLL_ISO);
+		clrbits32(plls[i].pwr_reg, PLL_ISO);
 
 	udelay(PLL_ISO_DELAY);
 
@@ -319,7 +319,7 @@ void mt_pll_init(void)
 
 	/* xPLL Frequency Enable */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		setbits_le32(plls[i].reg, PLL_EN);
+		setbits32(plls[i].reg, PLL_EN);
 
 	/* wait for PLL stable */
 	udelay(PLL_EN_DELAY);
@@ -327,32 +327,32 @@ void mt_pll_init(void)
 	/* xPLL DIV RSTB */
 	for (i = 0; i < APMIXED_PLL_MAX; i++) {
 		if (plls[i].rstb_shift != NO_RSTB_SHIFT)
-			setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
+			setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
 	}
 
 	/* MCUCFG CLKMUX */
-	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
-	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
-	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
 
-	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
-	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
-	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
 
 	/* enable infrasys DCM */
-	setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
-	clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl,
+	setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
+	clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl,
 		DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON);
-	setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
-	clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
-	clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl,
+	setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
+	clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
+	clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl,
 		DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON);
 
 	/* enable [11] for change i2c module source clock to TOPCKGEN */
-	setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
+	setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
 
 	/*
 	 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
@@ -361,19 +361,19 @@ void mt_pll_init(void)
 		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
 
 	/* enable [14] dramc_pll104m_ck */
-	setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 
 	/* enable audio clock */
-	setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
+	setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
 
 	/* enable intbus clock */
-	setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
+	setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
 
 	/* enable infra clock */
-	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
+	setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
 
 	/* enable mtkaif 26m clock */
-	setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
+	setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
 }
 
 void mt_pll_raise_ca53_freq(u32 freq)