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authorJarried Lin <jarried.lin@mediatek.corp-partner.google.com>2024-07-16 18:26:23 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-07-22 14:07:34 +0000
commita87649cee3883fd0044a212500487acd12912297 (patch)
tree1e2bd5c8b3aeb50aefd6269577184b4a755737c4 /src/soc/mediatek/mt8183/memlayout.ld
parentae37d6158efdae7f902ba058628b2115daee0b88 (diff)
soc/mediatek: Move memmory macros into MediaTek common directory
To reduce duplicate memmory macros of MediaTek SoCs, move the header file to a common directory. TEST=Build geralt pass BUG=b:317009620 Change-Id: Iea4add8fe3735085c13438a2e177bec177913191 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/memlayout.ld')
-rw-r--r--src/soc/mediatek/mt8183/memlayout.ld19
1 files changed, 1 insertions, 18 deletions
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index c5d9d08324..b1b9027798 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-/*
- * SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
- * It will be returned before starting the ramstage.
- * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
- */
-#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
-#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
-#define DRAM_INIT_CODE(addr, size) \
- REGION(dram_init_code, addr, size, 4)
-
-#define DRAM_DMA(addr, size) \
- REGION(dram_dma, addr, size, 4K) \
- _ = ASSERT(size % 4K == 0, \
- "DRAM DMA buffer should be multiple of smallest page size (4K)!");
+#include <soc/memlayout.h>
SECTIONS
{