diff options
author | Yanjie Jiang <yanjie.jiang@mediatek.com> | 2019-05-07 10:31:07 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-23 09:08:55 +0000 |
commit | 64dea2ed622156ef02eefd20d3e64dfdbf54bcb1 (patch) | |
tree | 3676e6ef144dee83b46baa7bc85e7a921f14802b /src/soc/mediatek/mt8183/md_ctrl.c | |
parent | cebf57905ba9d9b2850ef75758a135b18ec8e45c (diff) |
mediatek/mt8183: Add md power-off flow
SRCCLKENA holds 26M clock, which will fail suspend/resume,
and the SRCCLKENA is not used by mt8183,
so we can simply release it for suspend/resume to work.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui, suspend test pass.
Change-Id: Ib6e11faeb6936a1dd6bbe8b1a8b612446bf51082
Signed-off-by: Yanjie.jiang <yanjie.jiang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32666
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/md_ctrl.c')
-rw-r--r-- | src/soc/mediatek/mt8183/md_ctrl.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c new file mode 100644 index 0000000000..aa97756db2 --- /dev/null +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/md_ctrl.h> + +#define TOPCKGEN_CLK_MODE_MD_32K (1 << 8) +#define TOPCKGEN_CLK_MODE_MD_26M (1 << 9) +#define INFRA_MISC2_SRCCLKENA_RELEASE (0xFF) + +static void internal_md_power_down(void) +{ + /* Gating MD clock */ + setbits_le32(&mtk_topckgen->clk_mode, + TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M); + /* Release SRCCLKENA */ + clrbits_le32(&mt8183_infracfg->infra_misc2, + INFRA_MISC2_SRCCLKENA_RELEASE); +} + +void mtk_md_early_init(void) +{ + internal_md_power_down(); +} |