diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-05-06 11:05:15 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 08:38:20 +0000 |
| commit | 38779e6b8304cf4078bede5512ca07f609f3ea63 (patch) | |
| tree | 6f8886194ed3b818f282813829c77a010bddffbb /src/soc/mediatek/mt8183/include | |
| parent | 69d5bbf073ee45f18492a6204dc25c934c6d3c05 (diff) | |
soc/mediatek: improve ca53 frequency change procedure
To change frequency, the SOC PLL team suggests procedure below:
First, we need to enable the intermediate clock and
switch the ca53 clock source to the intermediate clock.
Second, disable the armpll_ll clock output.
Third, raise armpll_ll frequency and enable the clock output.
The last, switch the ca53 clock source back to armpll_ll and
disable the intermediate clock.
BUG=b:154451241
BRANCH=jacuzzi
TEST=Boots correctly on Jacuzzi.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 3fa7366942..3aa77c9f3b 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -217,6 +217,7 @@ enum { MUX_MASK = 0x3 << 9, MUX_SRC_ARMPLL = 0x1 << 9, + MUX_SRC_DIV_PLL1 = 0x2 << 9, }; enum { |